Timing

Timing of the SNES hardware.

Master Clock
The SNES master clock:
 * NTSC 21.447 MHz
 * PAL 21.281 MHz

CPU
A 65816 CPU "cycle" can take 6, 8 or 12 master cycles on the SNES, depending on the memory region accessed, and the MEMSEL fast-ROM setting.

This gives some commonly quoted SNES CPU speeds, though none of them tell a complete story:
 * 3.58 MHz fast-ROM (6-cycle)
 * 2.68 MHz slow-ROM (8-cycle)
 * 1.79 MHz other (12-cycle)

The speed of access depends on the memory region:
 * 6-cycles for fast-ROM access, enabled via MEMSEL and accessed at an address of $800000 of higher.
 * 8-cycles for slow-ROM access.
 * 8-cycles for internal S-WRAM.
 * 6-cycles for most MMIO registers.
 * 12-cycles for JOYSER0 and JOYSER1.
 * 6-cycles for "internal" cycles not accessing memory (e.g. 2nd cycle of NOP)

Video
Scanline:
 * 1364 master cycles = 341 dot cycles
 * The CPU pauses for 40 master cycles in the middle of each scanline.
 * Scanline 0 is the end of vblank and beginning of rendering. It is hidden, and displays as a blank line.
 * Scanlines 1-224 or 239 will normally render the visible image, unless force blanking is applied.
 * Scanline 261 or 311 is the last line of vertical blank (NTSC or PAL), after which the next frame begins rendering.
 * With interlacing on, 1 extra scanline will appear with each even frame, and one scanline outside the visible picture will be slightly shortened or lengthened for color synchronizatoin.

Vertical Blank: TODO
 * How much can we DMA during a vertical blank?
 * How many master cycles?

TODO How many master cycles per frame?

Tools

 * SnesInstructionCycleTool - calculates CPU cycles and master clock cycles under different conditions