SPC-700 instruction set

The Sony SPC-700 CPU is part of the S-SMP sound processor of the SNES. It runs at 1.024 MHz, and behaves similarly to a 6502 with some extensions.

Architecture
The SPC-700 has a 16-bit address space, and a similar set of registers to the 6502.

Registers

 * A - 8-bit accumulator
 * X - 8-bit index
 * Y - 8-bit index
 * YA - 16-bit pair of A (lsb) and Y (msb).
 * PC - program counter
 * SP - stack pointer
 * PSW - program status word: NVPBHIZC
 * N - negative flag (high bit of result was set)
 * V - overflow flag (signed overflow indication)
 * P - direct page flag (moves the direct page to $0100 if set)
 * H - half-carry flag (carry between low and high nibble)
 * I - interrupt enable (unused: the S-SMP has no attached interrupts)
 * Z - zero flag (set if last result was zero)
 * C - carry flag

Addressing Modes

 * imm - 8-bit immediate value
 * dp - 8-bit direct page offset ($0000+dp or $01000+dp)
 * !abs - 16-bit absolute address
 * rel - relative offset in two's complement
 * (i) - direct-page relative index (P * $100 + i)
 * (i)+ - direct-page relative index with post-increment (i is incremented after read)
 * [addr]+i - indirect indexed (add index after 16-bit lookup)
 * [addr+i] - indexed indirect (add index before 16-bit lookup)

Differences from the 6502

 * A 16-bit combined YA register is available for some operations.
 * The direct page can be moved to $0100. (Rarely used.)
 * No decimal mode, instead provides DAA and DAS instructions which use the added half-carry flag.
 * Interrupt status flag is enable, not disable. (Not important for SNES: there is no IRQ.)
 * Some operations allow direct page as a register-like destination, e.g. MOV dp, #imm or ADC dp, dp.
 * X or Y can be sometimes be used as an index to the direct page, possibly with an automatic post-increment, e.g. MOV (X)+ or ADC (X), (Y).
 * Multiply and divide instructions MUL and DIV</tt>.
 * Loop instructions CBNE</tt> and DBNZ</tt>.
 * Abbreviated call instructions for the high page of memory PCALL</tt> and TCALL</tt>.
 * Memory bit operations SET1</tt>, NOT1</tt>, MOV1</tt>, that can target individual bits of memory.
 * POP</tt> instructions do not modify flags (except POP PSW</tt>).
 * CALL</tt> places the address of the next instruction on the stack, rather than a pre-increment (-1) address like the 6502. RET</tt> similarly does not have a post-increment for the popped address.

Instructions
Official instruction names and syntax for SPC-700 instruction were provided by Sony. However, because of its architectural similarity to 6502, some prefer to rename and remap them using a 6502 style syntax. Both are provided here.

Sony instruction convention puts the destination on the left, source on the right (Intel syntax).

Cycles in this table are 1.024 MHz CPU cycles. Each one is equal to 2 clocks of the 2.048 MHz S-SMP.

Instruction list:
 * MOV</tt>
 * ADC</tt> SBC</tt> CMP</tt>
 * <tt>AND</tt> <tt>OR</tt> <tt>EOR</tt> <tt>ASL</tt> <tt>LSR</tt> <tt>ROL</tt> <tt>XCN</tt>
 * <tt>INC</tt> <tt>DEC</tt>
 * <tt>MOVW</tt> <tt>INCW</tt> <tt>DECW</tt> <tt>ADDW</tt> <tt>SUBW</tt> <tt>CMPW</tt> <tt>MUL</tt> <tt>DIV</tt>
 * <tt>DAA</tt> <tt>DAS</tt>
 * <tt>BRA</tt> <tt>BEQ</tt> <tt>BNE</tt> <tt>BCS</tt> <tt>BCC</tt> <tt>BVS</tt> <tt>BVC</tt> <tt>BMI</tt> <tt>BPL</tt> <tt>BBS</tt> <tt>BBC</tt> <tt>CBNE</tt> <tt>DBNZ</tt> <tt>JMP</tt>
 * <tt>CALL</tt> <tt>PCALL</tt> <tt>TCALL</tt> <tt>BRK</tt> <tt>RET</tt> <tt>RETI</tt>
 * <tt>PUSH</tt> <tt>POP</tt>
 * <tt>SET1</tt> <tt>CLR1</tt> <tt>TSET1</tt> <tt>TCLR1</tt> <tt>AND1</tt> <tt>OR1</tt> <tt>EOR1</tt> <tt>NOT1</tt> <tt>MOV1</tt>
 * <tt>CLRC</tt> <tt>SETC</tt> <tt>NOTC</tt> <tt>CLRV</tt> <tt>CLRP</tt> <tt>SETP</tt> <tt>EI</tt> <tt>DI</tt>
 * <tt>NOP</tt> <tt>SLEEP</tt> <tt>STOP</tt>

Links

 * SPC700 Reference - CPU Instruction Set at superfamicom.org wiki