Open bus

Where no device is connected to a data bus, the result is known as an open bus. This can happen at memory regions where no ROM or other device is mapped, or when reading from various registers for which some bits are open bus.

For the main CPU, the last value read on each data line will be retained, and reading from an open bus will simply repeat that value for its bit. In most cases this is the last byte of the instruction data fetched before the read (often the high byte of the read address), or for an indirect instruction it might be the high byte of the fetched indirect address.

The two PPU units each retain a separate open bus memory. Like with the main CPU, when a bit reads as "open bus" from either PPU, the value read will be a repeat of the last bit read from its bus.
 * PPU1 read addresses: $2134-$2136, $2138-$213A, $213E
 * PPU2 read addresses: $213B-$213D, $213F

PPU1 may also read the open bus value from any of the write-only registers at $21x4-$21x6 or $21x8-$21xA (x=0-2).