MMIO register table/PPU: Difference between revisions

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(importing table contents from PPU registers)
 
(sub screen CGWSEL is transparent)
 
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Line 1: Line 1:
<noinclude>
See: [[MMIO register table]]
{| class="wikitable"
! Name
! Address
! Bits
! Type
! Notes
|-
</noinclude>


! [[PPU registers#INIDISP|INIDISP]]
! [[PPU registers#INIDISP|INIDISP]]
! $2100
! $2100
| style="text-align: right" | <tt style="white-space: normal">F...&nbsp;BBBB</tt>
| style="text-align: right" | <tt style="white-space: nowrap">F... BBBB</tt>
| W8
| W8
| Forced blanking (F), screen brightness (B).
| Forced blanking (F), screen brightness (B).
|-
|-
! [[PPU registers#OBSEL|OBSEL]]
! [[PPU registers#OBJSEL|OBJSEL]]
! $2101
! $2101
| style="text-align: right" | <tt style="white-space: normal">SSSN&nbsp;NbBB</tt>
| style="text-align: right" | <tt style="white-space: nowrap">SSSN NbBB</tt>
| W8
| W8
| OBJ sprite size (S), name secondary select (N), name base address (B).
| OBJ sprite size (S), name secondary select (N), name base address (B).
Line 14: Line 24:
! [[PPU registers#OAMADD|OAMADDL]]<br/> [[PPU registers#OAMADD|OAMADDH]]
! [[PPU registers#OAMADD|OAMADDL]]<br/> [[PPU registers#OAMADD|OAMADDH]]
! $2102<br/> $2103
! $2102<br/> $2103
| style="text-align: right" | <tt style="white-space: normal">AAAA&nbsp;AAAA</tt><br/> <tt style="white-space: nowrap">P...&nbsp;...B</tt>
| style="text-align: right" | <tt style="white-space: nowrap">AAAA AAAA</tt><br/> <tt style="white-space: nowrap">P... ...B</tt>
| W16
| W16
| OAM word address (A).<br/> Priority rotation (P), address high bit (B).
| OAM word address (A).<br/> Priority rotation (P), address high bit (B).
Line 20: Line 30:
! [[PPU registers#OAMDATA|OAMDATA]]
! [[PPU registers#OAMDATA|OAMDATA]]
! $2104
! $2104
| style="text-align: right" | <tt style="white-space: normal">DDDD&nbsp;DDDD</tt>
| style="text-align: right" | <tt style="white-space: nowrap">DDDD DDDD</tt>
| W8x2
| W8x2
| OAM data write byte (2x for word) (D), increments OAMADD byte.
| OAM data write byte (2x for word) (D), increments OAMADD byte.
Line 26: Line 36:
! [[PPU registers#BGMODE|BGMODE]]
! [[PPU registers#BGMODE|BGMODE]]
! $2105
! $2105
| style="text-align: right" | <tt style="white-space: normal">4321&nbsp;PMMM</tt>
| style="text-align: right" | <tt style="white-space: nowrap">4321 PMMM</tt>
| W8
| W8
| Tilemap tile size (#), BG3 priority (P), BG mode (M).
| Tilemap tile size (#), BG3 priority (P), BG mode (M).
Line 32: Line 42:
! [[PPU registers#MOSAIC|MOSAIC]]
! [[PPU registers#MOSAIC|MOSAIC]]
! $2106
! $2106
| style="text-align: right" | <tt style="white-space: normal">SSSS&nbsp;4321</tt>
| style="text-align: right" | <tt style="white-space: nowrap">SSSS 4321</tt>
| W8
| W8
| Mosaic size (S), mosaic BG enable (#).
| Mosaic size (S), mosaic BG enable (#).
Line 38: Line 48:
! [[PPU registers#BGnSC|BG1SC]]<br/> [[PPU registers#BGnSC|BG2SC]]<br/> [[PPU registers#BGnSC|BG3SC]]<br/> [[PPU registers#BGnSC|BG4SC]]
! [[PPU registers#BGnSC|BG1SC]]<br/> [[PPU registers#BGnSC|BG2SC]]<br/> [[PPU registers#BGnSC|BG3SC]]<br/> [[PPU registers#BGnSC|BG4SC]]
! $2107<br/> $2108<br/> $2109<br/> $210A
! $2107<br/> $2108<br/> $2109<br/> $210A
| style="text-align: right" | <tt style="white-space: normal">AAAA&nbsp;AAYX</tt>
| style="text-align: right" | <tt style="white-space: nowrap">AAAA AAYX</tt>
| W8
| W8
| Tilemap VRAM address (A), vertical tilemap count (Y), horizontal tilemap count (X).
| Tilemap VRAM address (A), vertical tilemap count (Y), horizontal tilemap count (X).
Line 44: Line 54:
! [[PPU registers#BG12NBA|BG12NBA]]
! [[PPU registers#BG12NBA|BG12NBA]]
! $210B
! $210B
| style="text-align: right" | <tt style="white-space: normal">BBBB&nbsp;AAAA</tt>
| style="text-align: right" | <tt style="white-space: nowrap">BBBB AAAA</tt>
| W8
| W8
| BG2 CHR base address (B), BG1 CHR base address (A).
| BG2 CHR base address (B), BG1 CHR base address (A).
Line 50: Line 60:
! [[PPU registers#BG34NBA|BG34NBA]]
! [[PPU registers#BG34NBA|BG34NBA]]
! $210C
! $210C
| style="text-align: right" | <tt style="white-space: normal">DDDD&nbsp;CCCC</tt>
| style="text-align: right" | <tt style="white-space: nowrap">DDDD CCCC</tt>
| W8
| W8
| BG4 CHR base address (D), BG3 CHR base address (C).
| BG4 CHR base address (D), BG3 CHR base address (C).
Line 56: Line 66:
! [[PPU registers#BGnHOFS|BG1HOFS]]<br/> [[PPU registers#M7HOFS|M7HOFS]]<br/> [[PPU registers#BGnVOFS|BG1VOFS]]<br/> [[PPU registers#M7VOFS|M7VOFS]]
! [[PPU registers#BGnHOFS|BG1HOFS]]<br/> [[PPU registers#M7HOFS|M7HOFS]]<br/> [[PPU registers#BGnVOFS|BG1VOFS]]<br/> [[PPU registers#M7VOFS|M7VOFS]]
! $210D<br/> <br/> $210E
! $210D<br/> <br/> $210E
| style="text-align: right" | <tt style="white-space: normal">....&nbsp;..XX XXXX&nbsp;XXXX<br/> ...x&nbsp;xxxx xxxx&nbsp;xxxx<br/> ....&nbsp;..YY YYYY&nbsp;YYYY<br/> ...y&nbsp;yyyy yyyy&nbsp;yyyy</tt>
| style="text-align: right" | <tt style="white-space: nowrap">.... ..XX XXXX XXXX<br/> ...x xxxx xxxx xxxx<br/> .... ..YY YYYY YYYY<br/> ...y yyyy yyyy yyyy</tt>
| W8x2<br/> W8x2<br/> W8x2<br/> W8x2
| W8x2<br/> W8x2<br/> W8x2<br/> W8x2
| BG1 horizontal scroll (X).<br/> Mode 7 horizontal scroll (x).<br/> BG1 vertical scroll (Y).<br/> Mode 7 vertical scroll (y).
| BG1 horizontal scroll (X).<br/> Mode 7 horizontal scroll (x).<br/> BG1 vertical scroll (Y).<br/> Mode 7 vertical scroll (y).
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! [[PPU registers#BGnHOFS|BG2HOFS]]<br/> [[PPU registers#BGnVOFS|BG2VOFS]]<br/> [[PPU registers#BGnHOFS|BG3HOFS]]<br/> [[PPU registers#BGnVOFS|BG3VOFS]]<br/> [[PPU registers#BGnHOFS|BG4HOFS]]<br/> [[PPU registers#BGnVOFS|BG4VOFS]]
! [[PPU registers#BGnHOFS|BG2HOFS]]<br/> [[PPU registers#BGnVOFS|BG2VOFS]]<br/> [[PPU registers#BGnHOFS|BG3HOFS]]<br/> [[PPU registers#BGnVOFS|BG3VOFS]]<br/> [[PPU registers#BGnHOFS|BG4HOFS]]<br/> [[PPU registers#BGnVOFS|BG4VOFS]]
! $210F<br/> $2110<br/> $2111<br/> $2112<br/> $2113<br/> $2114
! $210F<br/> $2110<br/> $2111<br/> $2112<br/> $2113<br/> $2114
| style="text-align: right" | <tt style="white-space: normal">....&nbsp;..XX XXXX&nbsp;XXXX<br/> ....&nbsp;..YY YYYY&nbsp;YYYY</tt>
| style="text-align: right" | <tt style="white-space: nowrap">.... ..XX XXXX XXXX<br/> .... ..YY YYYY YYYY</tt>
| W8x2<br/> W8x2
| W8x2<br/> W8x2
| BG horizontal scroll (X).<br/> BG vertical scroll (Y).
| BG horizontal scroll (X).<br/> BG vertical scroll (Y).
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! [[PPU registers#VMAIN|VMAIN]]
! [[PPU registers#VMAIN|VMAIN]]
! $2115
! $2115
| style="text-align: right" | <tt style="white-space: normal">M...&nbsp;RRII</tt>
| style="text-align: right" | <tt style="white-space: nowrap">M... RRII</tt>
| W8
| W8
| VRAM address increment mode (M), remapping (R), increment size (I).
| VRAM address increment mode (M), remapping (R), increment size (I).
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! [[PPU registers#VMADD|VMADDL]]<br/> [[PPU registers#VMADD|VMADDH]]
! [[PPU registers#VMADD|VMADDL]]<br/> [[PPU registers#VMADD|VMADDH]]
! $2116<br/> $2117
! $2116<br/> $2117
| style="text-align: right" | <tt style="white-space: normal">LLLL&nbsp;LLLL</tt><br/> <tt style="white-space: nowrap">hHHH&nbsp;HHHH</tt>
| style="text-align: right" | <tt style="white-space: nowrap">LLLL LLLL</tt><br/> <tt style="white-space: nowrap">hHHH HHHH</tt>
| W16
| W16
| VRAM word address.
| VRAM word address.
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! [[PPU registers#VMDATA|VMDATAL]]<br/> [[PPU registers#VMDATA|VMDATAH]]
! [[PPU registers#VMDATA|VMDATAL]]<br/> [[PPU registers#VMDATA|VMDATAH]]
! $2118<br/> $2119
! $2118<br/> $2119
| style="text-align: right" | <tt style="white-space: normal">LLLL&nbsp;LLLL</tt><br/> <tt style="white-space: nowrap">HHHH&nbsp;HHHH</tt>
| style="text-align: right" | <tt style="white-space: nowrap">LLLL LLLL</tt><br/> <tt style="white-space: nowrap">HHHH HHHH</tt>
| W16
| W16
| VRAM data write. Increments VMADD after write according to VMAIN setting.
| VRAM data write. Increments VMADD after write according to VMAIN setting.
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! [[PPU registers#M7SEL|M7SEL]]
! [[PPU registers#M7SEL|M7SEL]]
! $211A
! $211A
| style="text-align: right" | <tt style="white-space: normal">RF..&nbsp;..YX</tt>
| style="text-align: right" | <tt style="white-space: nowrap">RF.. ..YX</tt>
| W8
| W8
| Mode 7 tilemap repeat (R), fill (F), flip vertical (Y), flip horizontal (X).
| Mode 7 tilemap repeat (R), fill (F), flip vertical (Y), flip horizontal (X).
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! [[PPU registers#M7A|M7A]]
! [[PPU registers#M7A|M7A]]
! $211B
! $211B
| style="text-align: right" | <tt style="white-space: normal">DDDD&nbsp;DDDD&nbsp;dddd&nbsp;dddd</tt>
| style="text-align: right" | <tt style="white-space: nowrap">DDDD DDDD dddd dddd</tt>
| W8x2
| W8x2
| Mode 7 matrix A or signed 16-bit multiplication factor.
| Mode 7 matrix A or signed 16-bit multiplication factor.
Line 98: Line 108:
! [[PPU registers#M7B|M7B]]
! [[PPU registers#M7B|M7B]]
! $211C
! $211C
| style="text-align: right" | <tt style="white-space: normal">DDDD&nbsp;DDDD&nbsp;dddd&nbsp;dddd</tt>
| style="text-align: right" | <tt style="white-space: nowrap">DDDD DDDD dddd dddd</tt>
| W8x2
| W8x2
| Mode 7 matrix B or signed 8-bit multiplication factor.
| Mode 7 matrix B or signed 8-bit multiplication factor.
Line 104: Line 114:
! [[PPU registers#M7n|M7C]]
! [[PPU registers#M7n|M7C]]
! $211D
! $211D
| style="text-align: right" | <tt style="white-space: normal">DDDD&nbsp;DDDD&nbsp;dddd&nbsp;dddd</tt>
| style="text-align: right" | <tt style="white-space: nowrap">DDDD DDDD dddd dddd</tt>
| W8x2
| W8x2
| Mode 7 matrix C
| Mode 7 matrix C
Line 110: Line 120:
! [[PPU registers#M7n|M7D]]
! [[PPU registers#M7n|M7D]]
! $211E
! $211E
| style="text-align: right" | <tt style="white-space: normal">DDDD&nbsp;DDDD&nbsp;dddd&nbsp;dddd</tt>
| style="text-align: right" | <tt style="white-space: nowrap">DDDD DDDD dddd dddd</tt>
| W8x2
| W8x2
| Mode 7 matrix D
| Mode 7 matrix D
Line 116: Line 126:
! [[PPU registers#M7X|M7X]]
! [[PPU registers#M7X|M7X]]
! $211F
! $211F
| style="text-align: right" | <tt style="white-space: normal">...X&nbsp;XXXX&nbsp;XXXX&nbsp;XXXX</tt>
| style="text-align: right" | <tt style="white-space: nowrap">...X XXXX XXXX XXXX</tt>
| W8x2
| W8x2
| Mode 7 center X
| Mode 7 center X
Line 122: Line 132:
! [[PPU registers#M7Y|M7Y]]
! [[PPU registers#M7Y|M7Y]]
! $2120
! $2120
| style="text-align: right" | <tt style="white-space: normal">...Y&nbsp;YYYY&nbsp;YYYY&nbsp;YYYY</tt>
| style="text-align: right" | <tt style="white-space: nowrap">...Y YYYY YYYY YYYY</tt>
| W8x2
| W8x2
| Mode 7 center Y
| Mode 7 center Y
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! [[PPU registers#CGADD|CGADD]]
! [[PPU registers#CGADD|CGADD]]
! $2121
! $2121
| style="text-align: right" | <tt style="white-space: normal">AAAA&nbsp;AAAA</tt>
| style="text-align: right" | <tt style="white-space: nowrap">AAAA AAAA</tt>
| W8
| W8
| CGRAM word address.
| CGRAM word address.
Line 134: Line 144:
! [[PPU registers#CGDATA|CGDATA]]
! [[PPU registers#CGDATA|CGDATA]]
! $2122
! $2122
| style="text-align: right" | <tt style="white-space: normal">.BBB&nbsp;BBGG&nbsp;GGGR&nbsp;RRRR</tt>
| style="text-align: right" | <tt style="white-space: nowrap">.BBB BBGG GGGR RRRR</tt>
| W8x2
| W8x2
| CGRAM data write, increments CGADD byte address after each write.
| CGRAM data write, increments CGADD byte address after each write.
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! [[PPU registers#W12SEL|W12SEL]]
! [[PPU registers#W12SEL|W12SEL]]
! $2123
! $2123
| style="text-align: right" | <tt style="white-space: normal">DdCc&nbsp;BbAa</tt>
| style="text-align: right" | <tt style="white-space: nowrap">DdCc BbAa</tt>
| W8
| W8
| Enable (ABCD) and Invert (abcd) windows for BG1 (AB) and BG2 (CD).
| Enable (ABCD) and Invert (abcd) windows for BG1 (AB) and BG2 (CD).
Line 146: Line 156:
! [[PPU registers#W34SEL|W34SEL]]
! [[PPU registers#W34SEL|W34SEL]]
! $2124
! $2124
| style="text-align: right" | <tt style="white-space: normal">DdCc&nbsp;BbAa</tt>
| style="text-align: right" | <tt style="white-space: nowrap">DdCc BbAa</tt>
| W8
| W8
| Enable (EFGH) and Invert (efgh) windows for BG3 (EF) and BG2 (GH).
| Enable (EFGH) and Invert (efgh) windows for BG3 (EF) and BG2 (GH).
Line 152: Line 162:
! [[PPU registers#WOBJSEL|WOBJSEL]]
! [[PPU registers#WOBJSEL|WOBJSEL]]
! $2125
! $2125
| style="text-align: right" | <tt style="white-space: normal">LlKk&nbsp;JjIi</tt>
| style="text-align: right" | <tt style="white-space: nowrap">LlKk JjIi</tt>
| W8
| W8
| Enable (IJKL) and Invert (ijkl) windows for OBJ (IJ) and color math (KL).
| Enable (IJKL) and Invert (ijkl) windows for OBJ (IJ) and color (KL).
|-
|-
! [[PPU registers#WH0|WH0]]
! [[PPU registers#WH0|WH0]]
! $2126
! $2126
| style="text-align: right" | <tt style="white-space: normal">LLLL&nbsp;LLLL</tt>
| style="text-align: right" | <tt style="white-space: nowrap">LLLL LLLL</tt>
| W8
| W8
| Window 1 left position.
| Window 1 left position.
Line 164: Line 174:
! [[PPU registers#WH1|WH1]]
! [[PPU registers#WH1|WH1]]
! $2127
! $2127
| style="text-align: right" | <tt style="white-space: normal">RRRR&nbsp;RRRR</tt>
| style="text-align: right" | <tt style="white-space: nowrap">RRRR RRRR</tt>
| W8
| W8
| Window 1 right position.
| Window 1 right position.
Line 170: Line 180:
! [[PPU registers#WH2|WH2]]
! [[PPU registers#WH2|WH2]]
! $2128
! $2128
| style="text-align: right" | <tt style="white-space: normal">LLLL&nbsp;LLLL</tt>
| style="text-align: right" | <tt style="white-space: nowrap">LLLL LLLL</tt>
| W8
| W8
| Window 2 left position.
| Window 2 left position.
Line 176: Line 186:
! [[PPU registers#WH3|WH3]]
! [[PPU registers#WH3|WH3]]
! $2129
! $2129
| style="text-align: right" | <tt style="white-space: normal">RRRR&nbsp;RRRR</tt>
| style="text-align: right" | <tt style="white-space: nowrap">RRRR RRRR</tt>
| W8
| W8
| Window 2 right position.
| Window 2 right position.
Line 182: Line 192:
! [[PPU registers#WBGLOG|WBGLOG]]
! [[PPU registers#WBGLOG|WBGLOG]]
! $212A
! $212A
| style="text-align: right" | <tt style="white-space: normal">4433&nbsp;2211</tt>
| style="text-align: right" | <tt style="white-space: nowrap">4433 2211</tt>
| W8
| W8
| Window mask logic for BG layers (00=OR, 01=AND, 10=XOR, 11=XNOR).
| Window mask logic for BG layers (00=OR, 01=AND, 10=XOR, 11=XNOR).
Line 188: Line 198:
! [[PPU registers#WOBJLOG|WOBJLOG]]
! [[PPU registers#WOBJLOG|WOBJLOG]]
! $212B
! $212B
| style="text-align: right" | <tt style="white-space: normal">....&nbsp;CCOO</tt>
| style="text-align: right" | <tt style="white-space: nowrap">.... CCOO</tt>
| W8
| W8
| Window mask logic for OBJ (O) and color math (C).
| Window mask logic for OBJ (O) and color (C).
|-
|-
! [[PPU registers#TM|TM]]
! [[PPU registers#TM|TM]]
! $212C
! $212C
| style="text-align: right" | <tt style="white-space: normal">...O&nbsp;4321</tt>
| style="text-align: right" | <tt style="white-space: nowrap">...O 4321</tt>
| W8
| W8
| Main screen layer enable (PPU registers#).
| Main screen layer enable (PPU registers#).
Line 200: Line 210:
! [[PPU registers#TS|TS]]
! [[PPU registers#TS|TS]]
! $212D
! $212D
| style="text-align: right" | <tt style="white-space: normal">...O&nbsp;4321</tt>
| style="text-align: right" | <tt style="white-space: nowrap">...O 4321</tt>
| W8
| W8
| Sub screen layer enable (#).
| Sub screen layer enable (#).
Line 206: Line 216:
! [[PPU registers#TMW|TMW]]
! [[PPU registers#TMW|TMW]]
! $212E
! $212E
| style="text-align: right" | <tt style="white-space: normal">...O&nbsp;4321</tt>
| style="text-align: right" | <tt style="white-space: nowrap">...O 4321</tt>
| W8
| W8
| Main screen layer window enable.
| Main screen layer window enable.
Line 212: Line 222:
! [[PPU registers#TSW|TSW]]
! [[PPU registers#TSW|TSW]]
! $212F
! $212F
| style="text-align: right" | <tt style="white-space: normal">...O&nbsp;4321</tt>
| style="text-align: right" | <tt style="white-space: nowrap">...O 4321</tt>
| W8
| W8
| Sub screen layer window enable.
| Sub screen layer window enable.
Line 218: Line 228:
! [[PPU registers#CGWSEL|CGWSEL]]
! [[PPU registers#CGWSEL|CGWSEL]]
! $2130
! $2130
| style="text-align: right" | <tt style="white-space: normal">BBMM&nbsp;..AD</tt>
| style="text-align: right" | <tt style="white-space: nowrap">MMSS ..AD</tt>
| W8
| W8
| Color addition black clip region (B), color math disable region (M), fixed/subscreen (A), direct color (D).
| main/sub screen color window black/transparent regions (MS), fixed/subscreen (A), direct color (D).
|-
|-
! [[PPU registers#CGADSUB|CGADSUB]]
! [[PPU registers#CGADSUB|CGADSUB]]
! $2131
! $2131
| style="text-align: right" | <tt style="white-space: normal">MHBO&nbsp;4321</tt>
| style="text-align: right" | <tt style="white-space: nowrap">MHBO 4321</tt>
| W8
| W8
| Color math add/subtract (M), half (H), backdrop (B), layer enable (O4321).
| Color math add/subtract (M), half (H), backdrop (B), layer enable (O4321).
Line 230: Line 240:
! [[PPU registers#COLDATA|COLDATA]]
! [[PPU registers#COLDATA|COLDATA]]
! $2132
! $2132
| style="text-align: right" | <tt style="white-space: normal">BGRC&nbsp;CCCC</tt>
| style="text-align: right" | <tt style="white-space: nowrap">BGRC CCCC</tt>
| W8
| W8
| Fixed color channel select (BGR) and value (C).
| Fixed color channel select (BGR) and value (C).
Line 236: Line 246:
! [[PPU registers#SETINI|SETINI]]
! [[PPU registers#SETINI|SETINI]]
! $2133
! $2133
| style="text-align: right" | <tt style="white-space: normal">EX..&nbsp;HOiI</tt>
| style="text-align: right" | <tt style="white-space: nowrap">EX.. HOiI</tt>
| W8
| W8
| External sync (E), EXTBG (X), Hi-res (H), Overscan (O), OBJ interlace (i), Screen interlace (I).
| External sync (E), EXTBG (X), Hi-res (H), Overscan (O), OBJ interlace (i), Screen interlace (I).
Line 242: Line 252:
! [[PPU registers#MPY|MPYL]]<br/> [[PPU registers#MPY|MPYM]]<br/> [[PPU registers#MPY|MPYH]]
! [[PPU registers#MPY|MPYL]]<br/> [[PPU registers#MPY|MPYM]]<br/> [[PPU registers#MPY|MPYH]]
! $2134<br/> $2135<br/> $2136
! $2134<br/> $2135<br/> $2136
| style="text-align: right" | <tt style="white-space: normal">LLLL&nbsp;LLLL</tt><br/> <tt style="white-space: normal">MMMM&nbsp;MMMM</tt><br/> <tt style="white-space: normal">HHHH&nbsp;HHHH</tt>
| style="text-align: right" | <tt style="white-space: nowrap">LLLL LLLL</tt><br/> <tt style="white-space: nowrap">MMMM MMMM</tt><br/> <tt style="white-space: nowrap">HHHH HHHH</tt>
| R24
| R24
| 24-bit signed multiplication result.
| 24-bit signed multiplication result.
Line 248: Line 258:
! [[PPU registers#SLHV|SLHV]]
! [[PPU registers#SLHV|SLHV]]
! $2137
! $2137
| style="text-align: right" | <tt style="white-space: normal">....&nbsp;....</tt><br/>
| style="text-align: right" | <tt style="white-space: nowrap">.... ....</tt><br/>
| R8
| R8
| Software latch for H/V counters.
| Software latch for H/V counters.
Line 254: Line 264:
! [[PPU registers#OAMDATAREAD|OAMDATAREAD]]
! [[PPU registers#OAMDATAREAD|OAMDATAREAD]]
! $2138
! $2138
| style="text-align: right" | <tt style="white-space: normal">DDDD&nbsp;DDDD</tt><br/>
| style="text-align: right" | <tt style="white-space: nowrap">DDDD DDDD</tt><br/>
| R8
| R8
| Read OAM data byte, increments OAMADD byte.
| Read OAM data byte, increments OAMADD byte.
Line 260: Line 270:
! [[PPU registers#VMDATAREAD|VMDATALREAD]]<br/> [[PPU registers#VMDATAREAD|VMDATAHREAD]]
! [[PPU registers#VMDATAREAD|VMDATALREAD]]<br/> [[PPU registers#VMDATAREAD|VMDATAHREAD]]
! $2139<br/> $213A
! $2139<br/> $213A
| style="text-align: right" | <tt style="white-space: normal">LLLL&nbsp;LLLL</tt><br/> <tt style="white-space: nowrap">HHHH&nbsp;HHHH</tt>
| style="text-align: right" | <tt style="white-space: nowrap">LLLL LLLL</tt><br/> <tt style="white-space: nowrap">HHHH HHHH</tt>
| R16
| R16
| VRAM data read. Increments VMADD after read according to VMAIN setting.
| VRAM data read. Increments VMADD after read according to VMAIN setting.
Line 266: Line 276:
! [[PPU registers#CGDATAREAD|CGDATAREAD]]
! [[PPU registers#CGDATAREAD|CGDATAREAD]]
! $213B
! $213B
| style="text-align: right" | <tt style="white-space: normal">.BBB&nbsp;BBGG&nbsp;GGGR&nbsp;RRRR</tt>
| style="text-align: right" | <tt style="white-space: nowrap">.BBB BBGG GGGR RRRR</tt>
| R8x2
| R8x2
| CGRAM data read, increments CGADD byte address after each write.
| CGRAM data read, increments CGADD byte address after each write.
Line 272: Line 282:
! [[PPU registers#OPHCT|OPHCT]]
! [[PPU registers#OPHCT|OPHCT]]
! $213C
! $213C
| style="text-align: right" | <tt style="white-space: normal">...H&nbsp;HHHH&nbsp;HHHH&nbsp;HHHH</tt>
| style="text-align: right" | <tt style="white-space: nowrap">...H HHHH HHHH HHHH</tt>
| R8x2
| R8x2
| Output horizontal counter.
| Output horizontal counter.
Line 278: Line 288:
! [[PPU registers#OPVCT|OPVCT]]
! [[PPU registers#OPVCT|OPVCT]]
! $213D
! $213D
| style="text-align: right" | <tt style="white-space: normal">...V&nbsp;VVVV&nbsp;VVVV&nbsp;VVVV</tt>
| style="text-align: right" | <tt style="white-space: nowrap">...V VVVV VVVV VVVV</tt>
| R8x2
| R8x2
| Output vertical counter.
| Output vertical counter.
Line 284: Line 294:
! [[PPU registers#STAT77|STAT77]]
! [[PPU registers#STAT77|STAT77]]
! $213E
! $213E
| style="text-align: right" | <tt style="white-space: normal">TRM.&nbsp;VVVV</tt><br/>
| style="text-align: right" | <tt style="white-space: nowrap">TRM. VVVV</tt><br/>
| R8
| R8
| Sprite overflow (T), sprite tile overflow (R), master/slave (M), PPU1 version (V).
| Sprite overflow (T), sprite tile overflow (R), master/slave (M), PPU1 version (V).
Line 290: Line 300:
! [[PPU registers#STAT78|STAT78]]
! [[PPU registers#STAT78|STAT78]]
! $213F
! $213F
| style="text-align: right" | <tt style="white-space: normal">FL.M&nbsp;VVVV</tt><br/>
| style="text-align: right" | <tt style="white-space: nowrap">FL.M VVVV</tt><br/>
| R8
| R8
| Interlace field (F), counter latch value (L), NTSC/PAL (M), PPU2 version (V).
| Interlace field (F), counter latch value (L), NTSC/PAL (M), PPU2 version (V).
|-
<noinclude>
|}
</noinclude>

Latest revision as of 01:49, 13 October 2022

See: MMIO register table

Name Address Bits Type Notes
INIDISP $2100 F... BBBB W8 Forced blanking (F), screen brightness (B).
OBJSEL $2101 SSSN NbBB W8 OBJ sprite size (S), name secondary select (N), name base address (B).
OAMADDL
OAMADDH 		$2102
$2103 		AAAA AAAA
P... ...B 		W16 OAM word address (A).
Priority rotation (P), address high bit (B).
OAMDATA $2104 DDDD DDDD W8x2 OAM data write byte (2x for word) (D), increments OAMADD byte.
BGMODE $2105 4321 PMMM W8 Tilemap tile size (#), BG3 priority (P), BG mode (M).
MOSAIC $2106 SSSS 4321 W8 Mosaic size (S), mosaic BG enable (#).
BG1SC
BG2SC
BG3SC
BG4SC 		$2107
$2108
$2109
$210A 		AAAA AAYX W8 Tilemap VRAM address (A), vertical tilemap count (Y), horizontal tilemap count (X).
BG12NBA $210B BBBB AAAA W8 BG2 CHR base address (B), BG1 CHR base address (A).
BG34NBA $210C DDDD CCCC W8 BG4 CHR base address (D), BG3 CHR base address (C).
BG1HOFS
M7HOFS
BG1VOFS
M7VOFS 		$210D

$210E 		.... ..XX XXXX XXXX
...x xxxx xxxx xxxx
.... ..YY YYYY YYYY
...y yyyy yyyy yyyy 		W8x2
W8x2
W8x2
W8x2 		BG1 horizontal scroll (X).
Mode 7 horizontal scroll (x).
BG1 vertical scroll (Y).
Mode 7 vertical scroll (y).
BG2HOFS
BG2VOFS
BG3HOFS
BG3VOFS
BG4HOFS
BG4VOFS 		$210F
$2110
$2111
$2112
$2113
$2114 		.... ..XX XXXX XXXX
.... ..YY YYYY YYYY 		W8x2
W8x2 		BG horizontal scroll (X).
BG vertical scroll (Y).
VMAIN $2115 M... RRII W8 VRAM address increment mode (M), remapping (R), increment size (I).
VMADDL
VMADDH 		$2116
$2117 		LLLL LLLL
hHHH HHHH 		W16 VRAM word address.
VMDATAL
VMDATAH 		$2118
$2119 		LLLL LLLL
HHHH HHHH 		W16 VRAM data write. Increments VMADD after write according to VMAIN setting.
M7SEL $211A RF.. ..YX W8 Mode 7 tilemap repeat (R), fill (F), flip vertical (Y), flip horizontal (X).
M7A $211B DDDD DDDD dddd dddd W8x2 Mode 7 matrix A or signed 16-bit multiplication factor.
M7B $211C DDDD DDDD dddd dddd W8x2 Mode 7 matrix B or signed 8-bit multiplication factor.
M7C $211D DDDD DDDD dddd dddd W8x2 Mode 7 matrix C
M7D $211E DDDD DDDD dddd dddd W8x2 Mode 7 matrix D
M7X $211F ...X XXXX XXXX XXXX W8x2 Mode 7 center X
M7Y $2120 ...Y YYYY YYYY YYYY W8x2 Mode 7 center Y
CGADD $2121 AAAA AAAA W8 CGRAM word address.
CGDATA $2122 .BBB BBGG GGGR RRRR W8x2 CGRAM data write, increments CGADD byte address after each write.
W12SEL $2123 DdCc BbAa W8 Enable (ABCD) and Invert (abcd) windows for BG1 (AB) and BG2 (CD).
W34SEL $2124 DdCc BbAa W8 Enable (EFGH) and Invert (efgh) windows for BG3 (EF) and BG2 (GH).
WOBJSEL $2125 LlKk JjIi W8 Enable (IJKL) and Invert (ijkl) windows for OBJ (IJ) and color (KL).
WH0 $2126 LLLL LLLL W8 Window 1 left position.
WH1 $2127 RRRR RRRR W8 Window 1 right position.
WH2 $2128 LLLL LLLL W8 Window 2 left position.
WH3 $2129 RRRR RRRR W8 Window 2 right position.
WBGLOG $212A 4433 2211 W8 Window mask logic for BG layers (00=OR, 01=AND, 10=XOR, 11=XNOR).
WOBJLOG $212B .... CCOO W8 Window mask logic for OBJ (O) and color (C).
TM $212C ...O 4321 W8 Main screen layer enable (PPU registers#).
TS $212D ...O 4321 W8 Sub screen layer enable (#).
TMW $212E ...O 4321 W8 Main screen layer window enable.
TSW $212F ...O 4321 W8 Sub screen layer window enable.
CGWSEL $2130 MMSS ..AD W8 main/sub screen color window black/transparent regions (MS), fixed/subscreen (A), direct color (D).
CGADSUB $2131 MHBO 4321 W8 Color math add/subtract (M), half (H), backdrop (B), layer enable (O4321).
COLDATA $2132 BGRC CCCC W8 Fixed color channel select (BGR) and value (C).
SETINI $2133 EX.. HOiI W8 External sync (E), EXTBG (X), Hi-res (H), Overscan (O), OBJ interlace (i), Screen interlace (I).
MPYL
MPYM
MPYH 		$2134
$2135
$2136 		LLLL LLLL
MMMM MMMM
HHHH HHHH 		R24 24-bit signed multiplication result.
SLHV $2137 .... ....
 R8 Software latch for H/V counters.
OAMDATAREAD $2138 DDDD DDDD
 R8 Read OAM data byte, increments OAMADD byte.
VMDATALREAD
VMDATAHREAD 		$2139
$213A 		LLLL LLLL
HHHH HHHH 		R16 VRAM data read. Increments VMADD after read according to VMAIN setting.
CGDATAREAD $213B .BBB BBGG GGGR RRRR R8x2 CGRAM data read, increments CGADD byte address after each write.
OPHCT $213C ...H HHHH HHHH HHHH R8x2 Output horizontal counter.
OPVCT $213D ...V VVVV VVVV VVVV R8x2 Output vertical counter.
STAT77 $213E TRM. VVVV
 R8 Sprite overflow (T), sprite tile overflow (R), master/slave (M), PPU1 version (V).
STAT78 $213F FL.M VVVV
 R8 Interlace field (F), counter latch value (L), NTSC/PAL (M), PPU2 version (V).
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