MMIO register table/DMA: Difference between revisions
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Rainwarrior (talk | contribs) (filling out table) |
Rainwarrior (talk | contribs) m (address increment mode (trying not to imply it's an enable)) |
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<noinclude> | <noinclude> | ||
See: [[ | See: [[MMIO register table]] | ||
{| class="wikitable" | {| class="wikitable" | ||
! Name | ! Name | ||
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| style="text-align: right" | <tt style="white-space: nowrap">DI.A APPP</tt> | | style="text-align: right" | <tt style="white-space: nowrap">DI.A APPP</tt> | ||
| RW8 | | RW8 | ||
| Direction (D), indirect HDMA (I), address increment (A), transfer pattern (P). | | Direction (D), indirect HDMA (I), address increment mode (A), transfer pattern (P). | ||
|- | |- | ||
! [[DMA registers#BBADn|BBADn]] | ! [[DMA registers#BBADn|BBADn]] | ||
| Line 23: | Line 23: | ||
| B-bus address. | | B-bus address. | ||
|- | |- | ||
! [[DMA registers#A1TnL|A1TnL]]<br/>[[DMA registers#A1TnH|A1TnH]]<br/>[[DMA registers# | ! [[DMA registers#A1TnL|A1TnL]]<br/>[[DMA registers#A1TnH|A1TnH]]<br/>[[DMA registers#A1Bn|A1Bn]] | ||
! $43n2<br/>$43n3<br/>$43n4 | ! $43n2<br/>$43n3<br/>$43n4 | ||
| style="text-align: right" | <tt style="white-space: nowrap">LLLL LLLL<br/>HHHH HHHH<br/>BBBB BBBB</tt> | | style="text-align: right" | <tt style="white-space: nowrap">LLLL LLLL<br/>HHHH HHHH<br/>BBBB BBBB</tt> | ||
| RW24 | | RW24 | ||
| DMA source address / HDMA table address. | | DMA source address / HDMA table start address. | ||
|- | |- | ||
! [[DMA registers#DASnL|DASnL]]<br/>[[DMA registers#DASnH|DASnH]]<br/>[[DMA registers# | ! [[DMA registers#DASnL|DASnL]]<br/>[[DMA registers#DASnH|DASnH]]<br/>[[DMA registers#DASBn|DASBn]] | ||
! $43n5<br/>$43n6<br/>$43n7 | ! $43n5<br/>$43n6<br/>$43n7 | ||
| style="text-align: right" | <tt style="white-space: nowrap">LLLL LLLL<br/>HHHH HHHH<br/>BBBB BBBB</tt> | | style="text-align: right" | <tt style="white-space: nowrap">LLLL LLLL<br/>HHHH HHHH<br/>BBBB BBBB</tt> | ||
| RW24 | | RW24 | ||
| DMA byte count (H:L) | | DMA byte count (H:L) / HDMA indirect table address (B:H:L). | ||
|- | |- | ||
! [[DMA registers#A2AnL|A2AnL]]<br/>[[DMA registers#A2AnH|A2AnH]] | ! [[DMA registers#A2AnL|A2AnL]]<br/>[[DMA registers#A2AnH|A2AnH]] | ||
| Line 41: | Line 41: | ||
| HDMA table current address within bank (H:L). | | HDMA table current address within bank (H:L). | ||
|- | |- | ||
! [[DMA registers# | ! [[DMA registers#NLTRn|NLTRn]] | ||
! $43nA | ! $43nA | ||
| style="text-align: right" | <tt style="white-space: nowrap">RLLL LLLL</tt> | | style="text-align: right" | <tt style="white-space: nowrap">RLLL LLLL</tt> | ||
| RW8 | | RW8 | ||
| HDMA reload (R) and scanline counter (L). | | HDMA reload flag (R) and scanline counter (L). | ||
|- | |- | ||
! [[DMA registers#UNUSEDn|UNUSEDn]] | ! [[DMA registers#UNUSEDn|UNUSEDn]] | ||
Latest revision as of 04:24, 11 October 2022
See: MMIO register table
| Name | Address | Bits | Type | Notes |
|---|---|---|---|---|
| DMAPn | $43n0 | DI.A APPP | RW8 | Direction (D), indirect HDMA (I), address increment mode (A), transfer pattern (P). |
| BBADn | $43n1 | AAAA AAAA | RW8 | B-bus address. |
| A1TnL A1TnH A1Bn |
$43n2 $43n3 $43n4 |
LLLL LLLL HHHH HHHH BBBB BBBB |
RW24 | DMA source address / HDMA table start address. |
| DASnL DASnH DASBn |
$43n5 $43n6 $43n7 |
LLLL LLLL HHHH HHHH BBBB BBBB |
RW24 | DMA byte count (H:L) / HDMA indirect table address (B:H:L). |
| A2AnL A2AnH |
$43n8 $43n9 |
LLLL LLLL HHHH HHHH |
RW16 | HDMA table current address within bank (H:L). |
| NLTRn | $43nA | RLLL LLLL | RW8 | HDMA reload flag (R) and scanline counter (L). |
| UNUSEDn | $43nB $43nF |
DDDD DDDD | RW8 | Unused shared data byte (D). |
