MMIO register table/DMA: Difference between revisions
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See: [[DMA register table]] | |||
{| class="wikitable" | {| class="wikitable" | ||
! Name | ! Name | ||
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! | |- | ||
! [[DMA registers#DMAPn|DMAPn]] | |||
! $43n0 | |||
| style="text-align: right" | <tt style="white-space: nowrap">DI.A APPP</tt> | |||
| RW8 | |||
| Direction (D), indirect HDMA (I), address increment (A), transfer pattern (P). | |||
|- | |||
! [[DMA registers#BBADn|BBADn]] | |||
! $43n1 | |||
| style="text-align: right" | <tt style="white-space: nowrap">AAAA AAAA</tt> | |||
| RW8 | |||
| B-bus address. | |||
|- | |||
! [[DMA registers#A1TnL|A1TnL]]<br/>[[DMA registers#A1TnH|A1TnH]]<br/>[[DMA registers#A1TnB|A1TnB]] | |||
! $43n2<br/>$43n3<br/>$43n4 | |||
| style="text-align: right" | <tt style="white-space: nowrap">LLLL LLLL<br/>HHHH HHHH<br/>BBBB BBBB</tt> | |||
| RW24 | |||
| DMA source address / HDMA table address. | |||
|- | |||
! [[DMA registers#DASnL|DASnL]]<br/>[[DMA registers#DASnH|DASnH]]<br/>[[DMA registers#DASnB|DASnB]] | |||
! $43n5<br/>$43n6<br/>$43n7 | |||
| style="text-align: right" | <tt style="white-space: nowrap">LLLL LLLL<br/>HHHH HHHH<br/>BBBB BBBB</tt> | |||
| RW24 | |||
| DMA byte count (H:L), HDMA table address (B:H:L). | |||
|- | |||
! [[DMA registers#A2AnL|A2AnL]]<br/>[[DMA registers#A2AnH|A2AnH]] | |||
! $43n8<br/>$43n9 | |||
| style="text-align: right" | <tt style="white-space: nowrap">LLLL LLLL<br/>HHHH HHHH</tt> | |||
| RW16 | |||
| HDMA table current address within bank (H:L). | |||
|- | |||
! [[DMA registers#NTRLn|NTRLn]] | |||
! $43nA | |||
| style="text-align: right" | <tt style="white-space: nowrap">RLLL LLLL</tt> | |||
| RW8 | |||
| HDMA reload (R) and scanline counter (L). | |||
|- | |||
! [[DMA registers#UNUSEDn|UNUSEDn]] | |||
! $43nB<br/>$43nF | |||
| style="text-align: right" | <tt style="white-space: nowrap">DDDD DDDD</tt> | |||
| RW8 | |||
| Unused shared data byte (D). | |||
|- | |||
<noinclude> | <noinclude> | ||
|} | |} | ||
</noinclude> | </noinclude> | ||
Revision as of 23:33, 23 May 2022
See: DMA register table
| Name | Address | Bits | Type | Notes |
|---|---|---|---|---|
| DMAPn | $43n0 | DI.A APPP | RW8 | Direction (D), indirect HDMA (I), address increment (A), transfer pattern (P). |
| BBADn | $43n1 | AAAA AAAA | RW8 | B-bus address. |
| A1TnL A1TnH A1TnB |
$43n2 $43n3 $43n4 |
LLLL LLLL HHHH HHHH BBBB BBBB |
RW24 | DMA source address / HDMA table address. |
| DASnL DASnH DASnB |
$43n5 $43n6 $43n7 |
LLLL LLLL HHHH HHHH BBBB BBBB |
RW24 | DMA byte count (H:L), HDMA table address (B:H:L). |
| A2AnL A2AnH |
$43n8 $43n9 |
LLLL LLLL HHHH HHHH |
RW16 | HDMA table current address within bank (H:L). |
| NTRLn | $43nA | RLLL LLLL | RW8 | HDMA reload (R) and scanline counter (L). |
| UNUSEDn | $43nB $43nF |
DDDD DDDD | RW8 | Unused shared data byte (D). |
