MMIO register table/DMA: Difference between revisions
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See: [[DMA | See: [[DMA registers]] | ||
{| class="wikitable" | {| class="wikitable" | ||
! Name | ! Name |
Revision as of 23:33, 23 May 2022
See: DMA registers
Name | Address | Bits | Type | Notes |
---|---|---|---|---|
DMAPn | $43n0 | DI.A APPP | RW8 | Direction (D), indirect HDMA (I), address increment (A), transfer pattern (P). |
BBADn | $43n1 | AAAA AAAA | RW8 | B-bus address. |
A1TnL A1TnH A1TnB |
$43n2 $43n3 $43n4 |
LLLL LLLL HHHH HHHH BBBB BBBB |
RW24 | DMA source address / HDMA table address. |
DASnL DASnH DASnB |
$43n5 $43n6 $43n7 |
LLLL LLLL HHHH HHHH BBBB BBBB |
RW24 | DMA byte count (H:L), HDMA table address (B:H:L). |
A2AnL A2AnH |
$43n8 $43n9 |
LLLL LLLL HHHH HHHH |
RW16 | HDMA table current address within bank (H:L). |
NTRLn | $43nA | RLLL LLLL | RW8 | HDMA reload (R) and scanline counter (L). |
UNUSEDn | $43nB $43nF |
DDDD DDDD | RW8 | Unused shared data byte (D). |