HDMA examples: Difference between revisions
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Examples for using HDMA. | Examples for using HDMA. | ||
== Transfer patterns == | |||
The following is a suggested list of PPU registers that can be used in the various HDMA transfer patterns. | |||
=== One register (DMAP pattern 0) === | |||
This pattern reads/writes a single byte to a single address on the B-bus (<code>+0</code>). | |||
This pattern should not be used on write-twice or read-twice registers. | |||
* BG Mode: <code>BGMODE</code> | |||
* Mosaic Settings: <code>MOSAIC</code> | |||
* BG Settings: <code>BG1SC</code>, <code>BG2SC</code>, <code>BG3SC</code>, <code>BG4SC</code>, <code>BG12NBA</code>, <code>BG34NBA</code> | |||
* Mode 7 settings: <code>M7SEL</code> | |||
* CGRAM address: <code>CGADD</code> | |||
** A future HDMA channel should write to <code>CGDATA</code> on the same scanline as the <code>CGADD</code> write. | |||
* Window settings: <code>W12SEL</code>, <code>W34SEL</code>, <code>WOBJSEL</code>, <code>WBGLOG</code>, <code>WOBJLOG</code> | |||
* Layer enable: <code>TM</code>, <code>TS</code>, <code>TMW</code>, <code>TSW</code> | |||
* Color math: <code>CGWSEL</code>, <code>CGADSUB</code> | |||
* Screen Mode/Video Select: <code>SETINI</code> | |||
* Fixed color data: <code>COLDATA</code> | |||
** Only a single B/G/R channel can be changed in this pattern (unless multiple channels contain the same value). See <code>[[PPU_registers#COLDATA|COLDATA]]</code> for more details. | |||
=== Two registers (DMAP pattern 1) === | |||
This pattern reads/writes two bytes to two addresses on the B-bus (<code>+0, +1</code>). It is useful when writing to two adjacent byte registers. | |||
This pattern must not be used on write-twice or read-twice registers. | |||
* Window 1 left and right position: <code>WH0</code> & <code>WH1</code> | |||
* Window 2 left and right position: <code>WH2</code> & <code>WH3</code> | |||
* Window mask settings: <code>W12SEL</code> & <code>W34SEL</code>, <code>W34SEL</code> & <code>WOBJSEL</code> | |||
* Window mask logic: <code>WBGLOG</code> & <code>WOBJLOG</code> | |||
* Layer Enable: <code>TM</code> & <code>TS</code>, <code>TMW</code> & <code>TSW</code> | |||
* Color math settings: <code>CGWSEL</code> & <code>CGADSUB</code> | |||
=== One register, write twice (DMAP pattern 2) === | |||
This pattern reads/writes two bytes to a single write-twice or read-twice register on the B-bus (<code>+0, +0</code>). | |||
* BG horizontal scroll offset: <code>BGnHOFS</code> | |||
* BG vertical scroll offset: <code>BGnVOFS</code> | |||
* Mode 7 matrix: <code>M7A</code>, <code>M7B</code>, <code>M7C</code>, <code>M7D</code>, <code>M7X</code>, <code>M7Y</code> | |||
* CGRAM data: <code>CGDATA</code> | |||
** Note: A previous HDMA channel should set the CGRAM address on the same scanline as a <code>CGDATA</code> write | |||
* Fixed color data: <code>COLDATA</code> | |||
** Only two of the three B/G/R channels can be changed in this pattern (unless two channels share the same value). See <code>[[PPU_registers#COLDATA|COLDATA]]</code> for more details. | |||
=== Two registers, write twice (DMAP pattern 3) === | |||
This pattern reads/writes four bytes to two adjacent write-twice or read-twice registers on the B-bus (<code>+0, +0, +1, +1</code>). | |||
* BG scroll offsets: <code>BGnHOFS</code> & <code>BGnVOFS</code> | |||
* 2 adjacent mode 7 matrix values: <code>M7A</code> & <code>M7B</code>, <code>M7C</code> & <code>M7D</code>, <code>M7X</code> & <code>M7Y</code> | |||
* CGRAM address and data: <code>CGADD</code> & <code>CGDATA</code> | |||
** This transfer will write two values to the CGRAM address, followed by a color word value to <code>CGDATA</code>. | |||
** The first byte will be ignored by the PPU, the second byte contains the target CGRAM address (palette index), the third and forth bytes contain the color data. | |||
=== Four registers (DMAP pattern 4) === | |||
This pattern reads/writes four bytes to four addresses on the B-bus (<code>+0, +1, +2, +3</code>). | |||
This pattern must not be used on write-twice or read-twice registers. | |||
* All four window positions: <code>WH0</code> & <code>WH1</code> & <code>WH2</code> & <code>WH3</code> | |||
== Links == | == Links == | ||
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* [https://nesdoug.com/2020/06/14/hdma-examples/ HDMA Examples] - by nesdoug | * [https://nesdoug.com/2020/06/14/hdma-examples/ HDMA Examples] - by nesdoug | ||
* [https://wiki.superfamicom.org/grog%27s-guide-to-dma-and-hdma-on-the-snes Grog's Guide to DMA and HDMA on the SNES] - superfamicom.org wiki | * [https://wiki.superfamicom.org/grog%27s-guide-to-dma-and-hdma-on-the-snes Grog's Guide to DMA and HDMA on the SNES] - superfamicom.org wiki | ||
[[Category:Graphics]] | [[Category:Graphics]] | ||
Revision as of 08:29, 7 November 2022
Examples for using HDMA.
Transfer patterns
The following is a suggested list of PPU registers that can be used in the various HDMA transfer patterns.
One register (DMAP pattern 0)
This pattern reads/writes a single byte to a single address on the B-bus (+0).
This pattern should not be used on write-twice or read-twice registers.
- BG Mode:
BGMODE - Mosaic Settings:
MOSAIC - BG Settings:
BG1SC,BG2SC,BG3SC,BG4SC,BG12NBA,BG34NBA - Mode 7 settings:
M7SEL - CGRAM address:
CGADD- A future HDMA channel should write to
CGDATAon the same scanline as theCGADDwrite.
- A future HDMA channel should write to
- Window settings:
W12SEL,W34SEL,WOBJSEL,WBGLOG,WOBJLOG - Layer enable:
TM,TS,TMW,TSW - Color math:
CGWSEL,CGADSUB - Screen Mode/Video Select:
SETINI - Fixed color data:
COLDATA- Only a single B/G/R channel can be changed in this pattern (unless multiple channels contain the same value). See
COLDATAfor more details.
- Only a single B/G/R channel can be changed in this pattern (unless multiple channels contain the same value). See
Two registers (DMAP pattern 1)
This pattern reads/writes two bytes to two addresses on the B-bus (+0, +1). It is useful when writing to two adjacent byte registers.
This pattern must not be used on write-twice or read-twice registers.
- Window 1 left and right position:
WH0&WH1 - Window 2 left and right position:
WH2&WH3 - Window mask settings:
W12SEL&W34SEL,W34SEL&WOBJSEL - Window mask logic:
WBGLOG&WOBJLOG - Layer Enable:
TM&TS,TMW&TSW - Color math settings:
CGWSEL&CGADSUB
One register, write twice (DMAP pattern 2)
This pattern reads/writes two bytes to a single write-twice or read-twice register on the B-bus (+0, +0).
- BG horizontal scroll offset:
BGnHOFS - BG vertical scroll offset:
BGnVOFS - Mode 7 matrix:
M7A,M7B,M7C,M7D,M7X,M7Y - CGRAM data:
CGDATA- Note: A previous HDMA channel should set the CGRAM address on the same scanline as a
CGDATAwrite
- Note: A previous HDMA channel should set the CGRAM address on the same scanline as a
- Fixed color data:
COLDATA- Only two of the three B/G/R channels can be changed in this pattern (unless two channels share the same value). See
COLDATAfor more details.
- Only two of the three B/G/R channels can be changed in this pattern (unless two channels share the same value). See
Two registers, write twice (DMAP pattern 3)
This pattern reads/writes four bytes to two adjacent write-twice or read-twice registers on the B-bus (+0, +0, +1, +1).
- BG scroll offsets:
BGnHOFS&BGnVOFS - 2 adjacent mode 7 matrix values:
M7A&M7B,M7C&M7D,M7X&M7Y - CGRAM address and data:
CGADD&CGDATA- This transfer will write two values to the CGRAM address, followed by a color word value to
CGDATA. - The first byte will be ignored by the PPU, the second byte contains the target CGRAM address (palette index), the third and forth bytes contain the color data.
- This transfer will write two values to the CGRAM address, followed by a color word value to
Four registers (DMAP pattern 4)
This pattern reads/writes four bytes to four addresses on the B-bus (+0, +1, +2, +3).
This pattern must not be used on write-twice or read-twice registers.
- All four window positions:
WH0&WH1&WH2&WH3
Links
- HDMA Examples - by nesdoug
- Grog's Guide to DMA and HDMA on the SNES - superfamicom.org wiki
