MMIO register table/DMA: Difference between revisions

Revision as of 23:52, 23 May 2022

Name	Address	Bits	Type	Notes
DMAPn	$43n0	`DI.A APPP`	RW8	Direction (D), indirect HDMA (I), address increment (A), transfer pattern (P).
BBADn	$43n1	`AAAA AAAA`	RW8	B-bus address.
A1TnL A1TnH A1Bn	$43n2 $43n3 $43n4	`LLLL LLLL HHHH HHHH BBBB BBBB`	RW24	DMA source address / HDMA table address.
DASnL DASnH DASBn	$43n5 $43n6 $43n7	`LLLL LLLL HHHH HHHH BBBB BBBB`	RW24	DMA byte count (H:L), HDMA table address (B:H:L).
A2AnL A2AnH	$43n8 $43n9	`LLLL LLLL HHHH HHHH`	RW16	HDMA table current address within bank (H:L).
NTRLn	$43nA	`RLLL LLLL`	RW8	HDMA reload (R) and scanline counter (L).
UNUSEDn	$43nB $43nF	`DDDD DDDD`	RW8	Unused shared data byte (D).

@@ Line 23: / Line 23: @@
 | B-bus address.
 |-
-! [[DMA registers#A1TnL|A1TnL]]<br/>[[DMA registers#A1TnH|A1TnH]]<br/>[[DMA registers#A1TnB|A1TnB]]
+! [[DMA registers#A1TnL|A1TnL]]<br/>[[DMA registers#A1TnH|A1TnH]]<br/>[[DMA registers#A1Bn|A1Bn]]
 ! $43n2<br/>$43n3<br/>$43n4
 | style="text-align: right" | <tt style="white-space: nowrap">LLLL LLLL<br/>HHHH HHHH<br/>BBBB BBBB</tt>
@@ Line 29: / Line 29: @@
 | DMA source address / HDMA table address.
 |-
-! [[DMA registers#DASnL|DASnL]]<br/>[[DMA registers#DASnH|DASnH]]<br/>[[DMA registers#DASnB|DASnB]]
+! [[DMA registers#DASnL|DASnL]]<br/>[[DMA registers#DASnH|DASnH]]<br/>[[DMA registers#DASBn|DASBn]]
 ! $43n5<br/>$43n6<br/>$43n7
 | style="text-align: right" | <tt style="white-space: nowrap">LLLL LLLL<br/>HHHH HHHH<br/>BBBB BBBB</tt>