SPC-700 instruction set: Difference between revisions

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The Sony SPC-700 CPU is part of the [[S-SMP]] sound processor of the SNES. It runs at 2.048 MHz, and behaves similarly to a 6502 at 1.024 MHz with some extensions.
The Sony SPC-700 CPU is part of the [[S-SMP]] sound processor of the SNES. It runs at 1.024 MHz, and behaves similarly to a 6502 with some extensions.


== Architecture ==
== Architecture ==
Line 13: Line 13:
* '''PC''' - program counter
* '''PC''' - program counter
* '''SP''' - stack pointer
* '''SP''' - stack pointer
* '''PSW''' - program status word: NVPBHIZC
* '''PSW''' - program status word: <tt>NVPBHIZC</tt>
** '''N''' - negative flag (high bit of result was set)
** '''N''' - negative flag (high bit of result was set)
** '''V''' - overflow flag (signed overflow indication)
** '''V''' - overflow flag (signed overflow indication)
** '''P''' - direct page flag (moves the direct page to $0100 if set)
** '''P''' - direct page flag (moves the direct page to $0100 if set)
** '''H''' - half-carry flag (carry between low and high nibble)
** '''H''' - half-carry flag (carry between low and high nibble)
** '''I''' - interrupt disable (unused: the S-SMP has no attached interrupts)
** '''I''' - interrupt enable (unused: the S-SMP has no attached interrupts)
** '''Z''' - zero flag (set if last result was zero)
** '''Z''' - zero flag (set if last result was zero)
** '''C''' - carry flag
** '''C''' - carry flag
Differences from the 6502:
* A 16-bit combined YA register is available for some operations.
* The direct page can be moved to $0100. (Rarely used.)
* A half carry flag that is useful for nibble operations, can be cleared by CLRV.
* No decimal mode.


=== Addressing Modes ===
=== Addressing Modes ===


* imm - 8-bit immediate value
* imm - 8-bit immediate value
* dp - 8-bit direct page offset ($0000+dp or $01000+dp)
* dp - 8-bit direct page offset ($0000 + dp or $0100 + dp)
* !abs - 16-bit absolute address
* !abs - 16-bit absolute address
* rel - relative offset in two's complement
* rel - relative offset in two's complement
* (i) - direct-page relative index (P * $100 + i)
* (i) - direct-page relative index (P * $100 + i)
* (i)+ - direct-page relative index with post-increment (i is incremented after read)
* (i)+ - direct-page relative index with post-increment (i is incremented after read)
* [addr]+i - indirect indexed (add index after lookup)
* [addr]+i - indirect indexed (add index after 16-bit lookup)
* [addr+i] - indexed indirect (add index before lookup)
* [addr+i] - indexed indirect (add index before 16-bit lookup)
 
=== Differences from the 6502 ===
 
==== Removed from SPC700 ====
 
* Decimal mode is missing; instead, <tt>DAA</tt> and <tt>DAS</tt> instructions which use the added half-carry flag are provided.
* The indirect ''non''-indexed variant of <tt>JMP</tt>.
* The <tt>LDX abs, Y</tt> and <tt>LDY abs, X</tt> instructions.
* The <tt>BIT</tt> instruction.
* <tt>abs, X</tt> modes in read-modify-write instructions: <tt>INC</tt>, <tt>DEC</tt>, <tt>ASL</tt>, <tt>LSR</tt>, <tt>ROL</tt>, <tt>ROR</tt>. (The <tt>zp, X</tt> and <tt>abs</tt> modes are available).
 
==== New to SPC700 ====
 
* The direct page can be moved to $0100. (Rarely used.)
* 16-bit operations, using either the direct page or the new 16-bit register YA:
** <tt>MOVW</tt>, <tt>ADDW</tt>, <tt>SUBW</tt>, <tt>CMPW</tt>, <tt>INCW</tt>, <tt>DECW</tt>.
** <tt>MUL</tt>, <tt>DIV</tt>: multiply/divide instructions.
* <tt>CBNE</tt>, <tt>DBNZ</tt>: loop instructions.
* <tt>PCALL</tt>, <tt>TCALL</tt>: abbreviated call instructions for the high page of memory.
* <tt>SET1</tt>, <tt>NOT1</tt>, <tt>MOV1</tt>, <tt>AND1</tt>, <tt>OR1</tt>, <tt>EOR1</tt>: single-bit operations on the lower 8KB of memory.
* <tt>XCN A</tt>: nibble exchange.
 
New addressing modes:
 
* Load/store, arithmetic and boolean operations have added the following modes:
** Direct page <- Immediate: <tt>MOV dp, #imm</tt>
** Direct page <- Direct page: <tt>AND dp, dp</tt>
** A <- Direct page pointer in X: <tt>OR A, (X)</tt>
** Direct page pointer in X <- Direct page pointer in Y: <tt>EOR (X), (Y)</tt>
* Load/store operations have added these additional modes:
** Direct page pointer in X, post-increment: <tt>MOV (X)+</tt>
 
Note that some features, despite not being available in the original 6502, have been previously introduced by the 65C02:
 
* <tt>BBC</tt>, <tt>BBS</tt>: branch on an individual bit set/clear in direct page locations.
* <tt>BRA</tt>: branch always.
* <tt>INC</tt>, <tt>DEC</tt> for the accumulator.
* <tt>RMB</tt>, <tt>SMB</tt>: set/clear an individual bit in direct page locations.
* The indirect indexed variant of <tt>JMP</tt>.
* The ability to directly push and pop <tt>X</tt> and <tt>Y</tt>.
 
==== Changed in SPC700 ====
 
* Interrupt status flag is enable, not disable. (Not important for SNES: there is no IRQ.)
* The cycle timings of many instructions are slightly different.
* <tt>POP</tt> instructions do not modify flags (except <tt>POP PSW</tt>).
* <tt>CALL</tt> places the address of the next instruction on the stack, rather than a pre-increment (-1) address like the 6502. <tt>RET</tt> similarly does not have a post-increment for the popped address.
* <tt>TSET1</tt> and <tt>TCLR1</tt> don't work like <tt>TSB</tt> and <tt>TRB</tt> on the 65C02: instead of using a bit test to set Z, the N/Z flags are set using an equality test.


== Instructions ==
== Instructions ==
Line 45: Line 87:
Sony instruction convention puts the destination on the left, source on the right (Intel syntax).
Sony instruction convention puts the destination on the left, source on the right (Intel syntax).


Cycles in this table are 1.024 MHz CPU cycles. Each one is equal to 2 clocks of the 2.048 Mhz S-SMP.
Cycles in this table are 1.024 MHz CPU cycles. Each one is equal to 2 clocks of the 2.048 MHz S-SMP.


{| class="wikitable sortable"
{| class="wikitable sortable"
Line 58: Line 100:
! Notes
! Notes
|-
|-
| colspan=7 | . 8-bit move memory to register
| colspan=7 | . '''8-bit move memory to register'''
|-
|-
| <tt>MOV A, #imm</tt>
| <tt>MOV A, #imm</tt>
Line 65: Line 107:
| 2
| 2
| 2
| 2
| <tt>N......Z</tt>
| <tt>N.....Z.</tt>
|
|
|-
|-
Line 73: Line 115:
| 1
| 1
| 3
| 3
| <tt>N......Z</tt>
| <tt>N.....Z.</tt>
|
|
|-
|-
Line 81: Line 123:
| 1
| 1
| 4
| 4
| <tt>N......Z</tt>
| <tt>N.....Z.</tt>
| X++ after read
| X++ after read
|-
|-
| <tt>MOV A, dp</tt>
| <tt>MOV A, dp</tt>
| <tt>LDA zp</tt>
| <tt>LDA dp</tt>
| <tt>E4</tt>
| <tt>E4</tt>
| 2
| 2
| 3
| 3
| <tt>N......Z</tt>
| <tt>N.....Z.</tt>
|
|
|-
|-
| <tt>MOV A, dp+X</tt>
| <tt>MOV A, dp+X</tt>
| <tt>LDA zp, X</tt>
| <tt>LDA dp, X</tt>
| <tt>F4</tt>
| <tt>F4</tt>
| 2
| 2
| 4
| 4
| <tt>N......Z</tt>
| <tt>N.....Z.</tt>
|
|
|-
|-
Line 105: Line 147:
| 3
| 3
| 4
| 4
| <tt>N......Z</tt>
| <tt>N.....Z.</tt>
|
|
|-
|-
Line 113: Line 155:
| 3
| 3
| 5
| 5
| <tt>N......Z</tt>
| <tt>N.....Z.</tt>
|
|
|-
|-
Line 121: Line 163:
| 3
| 3
| 5
| 5
| <tt>N......Z</tt>
| <tt>N.....Z.</tt>
|
|
|-
|-
| <tt>MOV A, [dp+X]</tt>
| <tt>MOV A, [dp+X]</tt>
| <tt>LDA (zp, X)</tt>
| <tt>LDA (dp, X)</tt>
| <tt>E7</tt>
| <tt>E7</tt>
| 2
| 2
| 6
| 6
| <tt>N......Z</tt>
| <tt>N.....Z.</tt>
|
|
|-
|-
Line 137: Line 179:
| 2
| 2
| 6
| 6
| <tt>N......Z</tt>
| <tt>N.....Z.</tt>
|
|
|-
|-
Line 145: Line 187:
| 2
| 2
| 2
| 2
| <tt>N......Z</tt>
| <tt>N.....Z.</tt>
|
|
|-
|-
| <tt>MOV X, dp</tt>
| <tt>MOV X, dp</tt>
| <tt>LDX zp</tt>
| <tt>LDX dp</tt>
| <tt>F8</tt>
| <tt>F8</tt>
| 2
| 2
| 3
| 3
| <tt>N......Z</tt>
| <tt>N.....Z.</tt>
|
|
|-
|-
| <tt>MOV X, dp+Y</tt>
| <tt>MOV X, dp+Y</tt>
| <tt>LDX zp, Y</tt>
| <tt>LDX dp, Y</tt>
| <tt>F9</tt>
| <tt>F9</tt>
| 2
| 2
| 4
| 4
| <tt>N......Z</tt>
| <tt>N.....Z.</tt>
|
|
|-
|-
Line 169: Line 211:
| 3
| 3
| 4
| 4
| <tt>N......Z</tt>
| <tt>N.....Z.</tt>
|
|


Line 178: Line 220:
| 2
| 2
| 2
| 2
| <tt>N......Z</tt>
| <tt>N.....Z.</tt>
|
|
|-
|-
| <tt>MOV Y, dp</tt>
| <tt>MOV Y, dp</tt>
| <tt>LDY zp</tt>
| <tt>LDY dp</tt>
| <tt>EB</tt>
| <tt>EB</tt>
| 2
| 2
| 3
| 3
| <tt>N......Z</tt>
| <tt>N.....Z.</tt>
|
|
|-
|-
| <tt>MOV Y, dp+X</tt>
| <tt>MOV Y, dp+X</tt>
| <tt>LDY zp, X</tt>
| <tt>LDY dp, X</tt>
| <tt>FB</tt>
| <tt>FB</tt>
| 2
| 2
| 4
| 4
| <tt>N......Z</tt>
| <tt>N.....Z.</tt>
|
|
|-
|-
Line 202: Line 244:
| 3
| 3
| 4
| 4
| <tt>N......Z</tt>
| <tt>N.....Z.</tt>
|
|
|-
|-
| colspan=7 | . 8-bit move register to memory
| colspan=7 | . '''8-bit move register to memory'''
|-
|-
| <tt>MOV (X), A</tt>
| <tt>MOV (X), A</tt>
Line 224: Line 266:
|-
|-
| <tt>MOV dp, A</tt>
| <tt>MOV dp, A</tt>
| <tt>STA zp</tt>
| <tt>STA dp</tt>
| <tt>C4</tt>
| <tt>C4</tt>
| 2
| 2
Line 232: Line 274:
|-
|-
| <tt>MOV dp+X, A</tt>
| <tt>MOV dp+X, A</tt>
| <tt>STA zp, X</tt>
| <tt>STA dp, X</tt>
| <tt>D4</tt>
| <tt>D4</tt>
| 2
| 2
Line 264: Line 306:
|-
|-
| <tt>MOV [dp+X], A</tt>
| <tt>MOV [dp+X], A</tt>
| <tt>STA (zp, X)</tt>
| <tt>STA (dp, X)</tt>
| <tt>C7</tt>
| <tt>C7</tt>
| 2
| 2
Line 272: Line 314:
|-
|-
| <tt>MOV [dp]+Y, A</tt>
| <tt>MOV [dp]+Y, A</tt>
| <tt>STA (zp), Y</tt>
| <tt>STA (dp), Y</tt>
| <tt>D7</tt>
| <tt>D7</tt>
| 2
| 2
Line 280: Line 322:
|-
|-
| <tt>MOV dp, X</tt>
| <tt>MOV dp, X</tt>
| <tt>STX zp</tt>
| <tt>STX dp</tt>
| <tt>D8</tt>
| <tt>D8</tt>
| 2
| 2
Line 288: Line 330:
|-
|-
| <tt>MOV dp+Y, X</tt>
| <tt>MOV dp+Y, X</tt>
| <tt>STX zp, Y</tt>
| <tt>STX dp, Y</tt>
| <tt>D9</tt>
| <tt>D9</tt>
| 2
| 2
Line 304: Line 346:
|-
|-
| <tt>MOV dp, Y</tt>
| <tt>MOV dp, Y</tt>
| <tt>STY zp</tt>
| <tt>STY dp</tt>
| <tt>CB</tt>
| <tt>CB</tt>
| 2
| 2
Line 312: Line 354:
|-
|-
| <tt>MOV dp+X, Y</tt>
| <tt>MOV dp+X, Y</tt>
| <tt>STY zp, X</tt>
| <tt>STY dp, X</tt>
| <tt>DB</tt>
| <tt>DB</tt>
| 2
| 2
Line 327: Line 369:
|
|
|-
|-
| colspan=7 | . 8-bit move register to register / special direct page moves
| colspan=7 | . '''8-bit move register to register / special direct page moves'''
|-
|-
| <tt>MOV A, X</tt>
| <tt>MOV A, X</tt>
Line 334: Line 376:
| 1
| 1
| 2
| 2
| <tt>N......Z</tt>
| <tt>N.....Z.</tt>
|
|
|-
|-
Line 342: Line 384:
| 1
| 1
| 2
| 2
| <tt>N......Z</tt>
| <tt>N.....Z.</tt>
|
|
|-
|-
Line 350: Line 392:
| 1
| 1
| 2
| 2
| <tt>N......Z</tt>
| <tt>N.....Z.</tt>
|
|
|-
|-
Line 358: Line 400:
| 1
| 1
| 2
| 2
| <tt>N......Z</tt>
| <tt>N.....Z.</tt>
|
|
|-
|-
Line 366: Line 408:
| 1
| 1
| 2
| 2
| <tt>N......Z</tt>
| <tt>N.....Z.</tt>
|
|
|-
|-
Line 393: Line 435:
|
|
|-
|-
| colspan=7 | TODO
| colspan=7 | . '''8-bit arithmetic'''
|-
| <tt>ADC A, #imm</tt>
| <tt>ADC #imm</tt>
| <tt>88</tt>
| 2
| 2
| <tt>NV..H.ZC</tt>
|
|-
| <tt>ADC A, (X)</tt>
| <tt>?</tt>
| <tt>86</tt>
| 1
| 3
| <tt>NV..H.ZC</tt>
|
|-
| <tt>ADC A, dp</tt>
| <tt>ADC dp</tt>
| <tt>84</tt>
| 2
| 3
| <tt>NV..H.ZC</tt>
|
|-
| <tt>ADC A, dp+X</tt>
| <tt>ADC dp, X</tt>
| <tt>94</tt>
| 2
| 4
| <tt>NV..H.ZC</tt>
|
|-
| <tt>ADC A, !abs</tt>
| <tt>ADC abs</tt>
| <tt>85</tt>
| 3
| 4
| <tt>NV..H.ZC</tt>
|
|-
| <tt>ADC A, !abs+X</tt>
| <tt>ADC abs, X</tt>
| <tt>95</tt>
| 3
| 5
| <tt>NV..H.ZC</tt>
|
|-
| <tt>ADC A, !abs+Y</tt>
| <tt>ADC abs, Y</tt>
| <tt>96</tt>
| 3
| 5
| <tt>NV..H.ZC</tt>
|
|-
| <tt>ADC A, [dp+X]</tt>
| <tt>ADC (dp, X)</tt>
| <tt>87</tt>
| 2
| 6
| <tt>NV..H.ZC</tt>
|
|-
| <tt>ADC A, [dp]+Y</tt>
| <tt>ADC (dp), Y</tt>
| <tt>97</tt>
| 2
| 6
| <tt>NV..H.ZC</tt>
|
|-
| <tt>ADC (X), (Y)</tt>
| <tt>?</tt>
| <tt>99</tt>
| 1
| 5
| <tt>NV..H.ZC</tt>
|
|-
| <tt>ADC dp, dp</tt>
| <tt>?</tt>
| <tt>89</tt>
| 3
| 6
| <tt>NV..H.ZC</tt>
|
|-
| <tt>ADC dp, #imm</tt>
| <tt>?</tt>
| <tt>98</tt>
| 3
| 5
| <tt>NV..H.ZC</tt>
|
|-
| <tt>SBC A, #imm</tt>
| <tt>SBC #imm</tt>
| <tt>A8</tt>
| 2
| 2
| <tt>NV..H.ZC</tt>
|
|-
| <tt>SBC A, (X)</tt>
| <tt>?</tt>
| <tt>A6</tt>
| 1
| 3
| <tt>NV..H.ZC</tt>
|
|-
| <tt>SBC A, dp</tt>
| <tt>SBC dp</tt>
| <tt>A4</tt>
| 2
| 3
| <tt>NV..H.ZC</tt>
|
|-
| <tt>SBC A, dp+X</tt>
| <tt>SBC dp, X</tt>
| <tt>B4</tt>
| 2
| 4
| <tt>NV..H.ZC</tt>
|
|-
| <tt>SBC A, !abs</tt>
| <tt>SBC abs</tt>
| <tt>A5</tt>
| 3
| 4
| <tt>NV..H.ZC</tt>
|
|-
| <tt>SBC A, !abs+X</tt>
| <tt>SBC abs, X</tt>
| <tt>B5</tt>
| 3
| 5
| <tt>NV..H.ZC</tt>
|
|-
| <tt>SBC A, !abs+Y</tt>
| <tt>SBC abs, Y</tt>
| <tt>B6</tt>
| 3
| 5
| <tt>NV..H.ZC</tt>
|
|-
| <tt>SBC A, [dp+X]</tt>
| <tt>SBC (dp, X)</tt>
| <tt>A7</tt>
| 2
| 6
| <tt>NV..H.ZC</tt>
|
|-
| <tt>SBC A, [dp]+Y</tt>
| <tt>SBC (dp), Y</tt>
| <tt>B7</tt>
| 2
| 6
| <tt>NV..H.ZC</tt>
|
|-
| <tt>SBC (X), (Y)</tt>
| <tt>?</tt>
| <tt>B9</tt>
| 1
| 5
| <tt>NV..H.ZC</tt>
|
|-
| <tt>SBC dp, dp</tt>
| <tt>?</tt>
| <tt>A9</tt>
| 3
| 6
| <tt>NV..H.ZC</tt>
|
|-
| <tt>SBC dp, #imm</tt>
| <tt>?</tt>
| <tt>B8</tt>
| 3
| 5
| <tt>NV..H.ZC</tt>
|
|-
| <tt>CMP A, #imm</tt>
| <tt>CMP #imm</tt>
| <tt>68</tt>
| 2
| 2
| <tt>N.....ZC</tt>
|
|-
| <tt>CMP A, (X)</tt>
| <tt>?</tt>
| <tt>66</tt>
| 1
| 3
| <tt>N.....ZC</tt>
|
|-
| <tt>CMP A, dp</tt>
| <tt>CMP dp</tt>
| <tt>64</tt>
| 2
| 3
| <tt>N.....ZC</tt>
|
|-
| <tt>CMP A, dp+X</tt>
| <tt>CMP dp, X</tt>
| <tt>74</tt>
| 2
| 4
| <tt>N.....ZC</tt>
|
|-
| <tt>CMP A, !abs</tt>
| <tt>CMP abs</tt>
| <tt>65</tt>
| 3
| 4
| <tt>N.....ZC</tt>
|
|-
| <tt>CMP A, !abs+X</tt>
| <tt>CMP abs, X</tt>
| <tt>75</tt>
| 3
| 5
| <tt>N.....ZC</tt>
|
|-
| <tt>CMP A, !abs+Y</tt>
| <tt>CMP abs, Y</tt>
| <tt>76</tt>
| 3
| 5
| <tt>N.....ZC</tt>
|
|-
| <tt>CMP A, [dp+X]</tt>
| <tt>CMP (dp, X)</tt>
| <tt>67</tt>
| 2
| 6
| <tt>N.....ZC</tt>
|
|-
| <tt>CMP A, [dp]+Y</tt>
| <tt>CMP (dp), Y</tt>
| <tt>77</tt>
| 2
| 6
| <tt>N.....ZC</tt>
|
|-
| <tt>CMP (X), (Y)</tt>
| <tt>?</tt>
| <tt>79</tt>
| 1
| 5
| <tt>N.....ZC</tt>
|
|-
| <tt>CMP dp, dp</tt>
| <tt>?</tt>
| <tt>69</tt>
| 3
| 6
| <tt>N.....ZC</tt>
|
|-
| <tt>CMP dp, #imm</tt>
| <tt>?</tt>
| <tt>78</tt>
| 3
| 5
| <tt>N.....ZC</tt>
|
|-
| <tt>CMP X, #imm</tt>
| <tt>CPX #imm</tt>
| <tt>C8</tt>
| 2
| 2
| <tt>N.....ZC</tt>
|
|-
| <tt>CMP X, dp</tt>
| <tt>CPX dp</tt>
| <tt>3E</tt>
| 2
| 3
| <tt>N.....ZC</tt>
|
|-
| <tt>CMP X, !abs</tt>
| <tt>CPX abs</tt>
| <tt>1E</tt>
| 3
| 4
| <tt>N.....ZC</tt>
|
|-
| <tt>CMP Y, #imm</tt>
| <tt>CPY #imm</tt>
| <tt>AD</tt>
| 2
| 2
| <tt>N.....ZC</tt>
|
|-
| <tt>CMP Y, dp</tt>
| <tt>CPY dp</tt>
| <tt>7E</tt>
| 2
| 3
| <tt>N.....ZC</tt>
|
|-
| <tt>CMP Y, !abs</tt>
| <tt>CPY abs</tt>
| <tt>5E</tt>
| 3
| 4
| <tt>N.....ZC</tt>
|
|-
| colspan=7 | . '''8-bit boolean logic'''
|-
| <tt>AND A, #imm</tt>
| <tt>AND #imm</tt>
| <tt>28</tt>
| 2
| 2
| <tt>N.....Z.</tt>
|
|-
| <tt>AND A, (X)</tt>
| <tt>?</tt>
| <tt>26</tt>
| 1
| 3
| <tt>N.....Z.</tt>
|
|-
| <tt>AND A, dp</tt>
| <tt>AND dp</tt>
| <tt>24</tt>
| 2
| 3
| <tt>N.....Z.</tt>
|
|-
| <tt>AND A, dp+X</tt>
| <tt>AND dp, X</tt>
| <tt>34</tt>
| 2
| 4
| <tt>N.....Z.</tt>
|
|-
| <tt>AND A, !abs</tt>
| <tt>AND abs</tt>
| <tt>25</tt>
| 3
| 4
| <tt>N.....Z.</tt>
|
|-
| <tt>AND A, !abs+X</tt>
| <tt>AND abs, X</tt>
| <tt>35</tt>
| 3
| 5
| <tt>N.....Z.</tt>
|
|-
| <tt>AND A, !abs+Y</tt>
| <tt>AND abs, Y</tt>
| <tt>36</tt>
| 3
| 5
| <tt>N.....Z.</tt>
|
|-
| <tt>AND A, [dp+X]</tt>
| <tt>AND (dp, X)</tt>
| <tt>27</tt>
| 2
| 6
| <tt>N.....Z.</tt>
|
|-
| <tt>AND A, [dp]+Y</tt>
| <tt>AND (dp), Y</tt>
| <tt>37</tt>
| 2
| 6
| <tt>N.....Z.</tt>
|
|-
| <tt>AND (X), (Y)</tt>
| <tt>?</tt>
| <tt>39</tt>
| 1
| 5
| <tt>N.....Z.</tt>
|
|-
| <tt>AND dp, dp</tt>
| <tt>?</tt>
| <tt>29</tt>
| 3
| 6
| <tt>N.....Z.</tt>
|
|-
| <tt>AND dp, #imm</tt>
| <tt>?</tt>
| <tt>38</tt>
| 3
| 5
| <tt>N.....Z.</tt>
|
|-
| <tt>OR A, #imm</tt>
| <tt>ORA #imm</tt>
| <tt>08</tt>
| 2
| 2
| <tt>N.....Z.</tt>
|
|-
| <tt>OR A, (X)</tt>
| <tt>?</tt>
| <tt>06</tt>
| 1
| 3
| <tt>N.....Z.</tt>
|
|-
| <tt>OR A, dp</tt>
| <tt>ORA dp</tt>
| <tt>04</tt>
| 2
| 3
| <tt>N.....Z.</tt>
|
|-
| <tt>OR A, dp+X</tt>
| <tt>ORA dp, X</tt>
| <tt>14</tt>
| 2
| 4
| <tt>N.....Z.</tt>
|
|-
| <tt>OR A, !abs</tt>
| <tt>ORA abs</tt>
| <tt>05</tt>
| 3
| 4
| <tt>N.....Z.</tt>
|
|-
| <tt>OR A, !abs+X</tt>
| <tt>ORA abs, X</tt>
| <tt>15</tt>
| 3
| 5
| <tt>N.....Z.</tt>
|
|-
| <tt>OR A, !abs+Y</tt>
| <tt>ORA abs, Y</tt>
| <tt>16</tt>
| 3
| 5
| <tt>N.....Z.</tt>
|
|-
| <tt>OR A, [dp+X]</tt>
| <tt>ORA (dp, X)</tt>
| <tt>07</tt>
| 2
| 6
| <tt>N.....Z.</tt>
|
|-
| <tt>OR A, [dp]+Y</tt>
| <tt>ORA (dp), Y</tt>
| <tt>17</tt>
| 2
| 6
| <tt>N.....Z.</tt>
|
|-
| <tt>OR (X), (Y)</tt>
| <tt>?</tt>
| <tt>19</tt>
| 1
| 5
| <tt>N.....Z.</tt>
|
|-
| <tt>OR dp, dp</tt>
| <tt>?</tt>
| <tt>09</tt>
| 3
| 6
| <tt>N.....Z.</tt>
|
|-
| <tt>OR dp, #imm</tt>
| <tt>?</tt>
| <tt>18</tt>
| 3
| 5
| <tt>N.....Z.</tt>
|
|-
| <tt>EOR A, #imm</tt>
| <tt>EOR #imm</tt>
| <tt>48</tt>
| 2
| 2
| <tt>N.....Z.</tt>
|
|-
| <tt>EOR A, (X)</tt>
| <tt>?</tt>
| <tt>46</tt>
| 1
| 3
| <tt>N.....Z.</tt>
|
|-
| <tt>EOR A, dp</tt>
| <tt>EOR dp</tt>
| <tt>44</tt>
| 2
| 3
| <tt>N.....Z.</tt>
|
|-
| <tt>EOR A, dp+X</tt>
| <tt>EOR dp, X</tt>
| <tt>54</tt>
| 2
| 4
| <tt>N.....Z.</tt>
|
|-
| <tt>EOR A, !abs</tt>
| <tt>EOR abs</tt>
| <tt>45</tt>
| 3
| 4
| <tt>N.....Z.</tt>
|
|-
| <tt>EOR A, !abs+X</tt>
| <tt>EOR abs, X</tt>
| <tt>55</tt>
| 3
| 5
| <tt>N.....Z.</tt>
|
|-
| <tt>EOR A, !abs+Y</tt>
| <tt>EOR abs, Y</tt>
| <tt>56</tt>
| 3
| 5
| <tt>N.....Z.</tt>
|
|-
| <tt>EOR A, [dp+X]</tt>
| <tt>EOR (dp, X)</tt>
| <tt>47</tt>
| 2
| 6
| <tt>N.....Z.</tt>
|
|-
| <tt>EOR A, [dp]+Y</tt>
| <tt>EOR (dp), Y</tt>
| <tt>57</tt>
| 2
| 6
| <tt>N.....Z.</tt>
|
|-
| <tt>EOR (X), (Y)</tt>
| <tt>?</tt>
| <tt>59</tt>
| 1
| 5
| <tt>N.....Z.</tt>
|
|-
| <tt>EOR dp, dp</tt>
| <tt>?</tt>
| <tt>49</tt>
| 3
| 6
| <tt>N.....Z.</tt>
|
|-
| <tt>EOR dp, #imm</tt>
| <tt>?</tt>
| <tt>58</tt>
| 3
| 5
| <tt>N.....Z.</tt>
|
|-
| colspan=7 | . '''8-bit increment / decrement'''
|-
| <tt>INC A</tt>
| <tt>INC</tt>
| <tt>BC</tt>
| 1
| 2
| <tt>N.....Z.</tt>
|
|-
| <tt>INC dp</tt>
| <tt>INC dp</tt>
| <tt>AB</tt>
| 2
| 4
| <tt>N.....Z.</tt>
|
|-
| <tt>INC dp+X</tt>
| <tt>INC dp, X</tt>
| <tt>BB</tt>
| 2
| 5
| <tt>N.....Z.</tt>
|
|-
| <tt>INC !abs</tt>
| <tt>INC abs</tt>
| <tt>AC</tt>
| 3
| 5
| <tt>N.....Z.</tt>
|
|-
| <tt>INC X</tt>
| <tt>INX</tt>
| <tt>3D</tt>
| 1
| 2
| <tt>N.....Z.</tt>
|
|-
| <tt>INC Y</tt>
| <tt>INY</tt>
| <tt>FC</tt>
| 1
| 2
| <tt>N.....Z.</tt>
|
|-
| <tt>DEC A</tt>
| <tt>DEC</tt>
| <tt>9C</tt>
| 1
| 2
| <tt>N.....Z.</tt>
|
|-
| <tt>DEC dp</tt>
| <tt>DEC dp</tt>
| <tt>8B</tt>
| 2
| 4
| <tt>N.....Z.</tt>
|
|-
| <tt>DEC dp+X</tt>
| <tt>DEC dp, X</tt>
| <tt>9B</tt>
| 2
| 5
| <tt>N.....Z.</tt>
|
|-
| <tt>DEC !abs</tt>
| <tt>DEC abs</tt>
| <tt>8C</tt>
| 3
| 5
| <tt>N.....Z.</tt>
|
|-
| <tt>DEC X</tt>
| <tt>DEX</tt>
| <tt>1D</tt>
| 1
| 2
| <tt>N.....Z.</tt>
|
|-
| <tt>DEC Y</tt>
| <tt>DEY</tt>
| <tt>DC</tt>
| 1
| 2
| <tt>N.....Z.</tt>
|
|-
| colspan=7 | . '''8-bit shift / rotation'''
|-
| <tt>ASL A</tt>
| <tt>ASL</tt>
| <tt>1C</tt>
| 1
| 2
| <tt>N.....ZC</tt>
|
|-
| <tt>ASL dp</tt>
| <tt>ASL dp</tt>
| <tt>0B</tt>
| 2
| 4
| <tt>N.....ZC</tt>
|
|-
| <tt>ASL dp+X</tt>
| <tt>ASL dp, X</tt>
| <tt>1B</tt>
| 2
| 5
| <tt>N.....ZC</tt>
|
|-
| <tt>ASL !abs</tt>
| <tt>ASL abs</tt>
| <tt>0C</tt>
| 3
| 5
| <tt>N.....ZC</tt>
|
|-
| <tt>LSR A</tt>
| <tt>LSR</tt>
| <tt>5C</tt>
| 1
| 2
| <tt>N.....ZC</tt>
|
|-
| <tt>LSR dp</tt>
| <tt>LSR dp</tt>
| <tt>4B</tt>
| 2
| 4
| <tt>N.....ZC</tt>
|
|-
| <tt>LSR dp+X</tt>
| <tt>LSR dp, X</tt>
| <tt>5B</tt>
| 2
| 5
| <tt>N.....ZC</tt>
|
|-
| <tt>LSR !abs</tt>
| <tt>LSR abs</tt>
| <tt>4C</tt>
| 3
| 5
| <tt>N.....ZC</tt>
|
|-
| <tt>ROL A</tt>
| <tt>ROL</tt>
| <tt>3C</tt>
| 1
| 2
| <tt>N.....ZC</tt>
|
|-
| <tt>ROL dp</tt>
| <tt>ROL dp</tt>
| <tt>2B</tt>
| 2
| 4
| <tt>N.....ZC</tt>
|
|-
| <tt>ROL dp+X</tt>
| <tt>ROL dp, X</tt>
| <tt>3B</tt>
| 2
| 5
| <tt>N.....ZC</tt>
|
|-
| <tt>ROL !abs</tt>
| <tt>ROL abs</tt>
| <tt>2C</tt>
| 3
| 5
| <tt>N.....ZC</tt>
|
|-
| <tt>ROR A</tt>
| <tt>ROR</tt>
| <tt>7C</tt>
| 1
| 2
| <tt>N.....ZC</tt>
|
|-
| <tt>ROR dp</tt>
| <tt>ROR dp</tt>
| <tt>6B</tt>
| 2
| 4
| <tt>N.....ZC</tt>
|
|-
| <tt>ROR dp+X</tt>
| <tt>ROR dp, X</tt>
| <tt>7B</tt>
| 2
| 5
| <tt>N.....ZC</tt>
|
|-
| <tt>ROR !abs</tt>
| <tt>ROR abs</tt>
| <tt>6C</tt>
| 3
| 5
| <tt>N.....ZC</tt>
|
|-
| <tt>XCN A</tt>
| <tt>?</tt>
| <tt>9F</tt>
| 1
| 5
| <tt>N.....Z.</tt>
| Exchange nibbles of A
|-
| colspan=7 | . '''16-bit operations'''
|-
| <tt>MOVW YA, dp</tt>
| <tt>?</tt>
| <tt>BA</tt>
| 2
| 5
| <tt>N.....Z.</tt>
|
|-
| <tt>MOVW dp, YA</tt>
| <tt>?</tt>
| <tt>DA</tt>
| 2
| 4
| <tt>........</tt>
|
|-
| <tt>INCW dp</tt>
| <tt>?</tt>
| <tt>3A</tt>
| 2
| 6
| <tt>N.....Z.</tt>
|
|-
| <tt>DECW dp</tt>
| <tt>?</tt>
| <tt>1A</tt>
| 2
| 6
| <tt>N.....Z.</tt>
|
|-
| <tt>ADDW YA, dp</tt>
| <tt>?</tt>
| <tt>7A</tt>
| 2
| 5
| <tt>NV..H.ZC</tt>
| Uses carry flag
|-
| <tt>SUBW YA, dp</tt>
| <tt>?</tt>
| <tt>9A</tt>
| 2
| 5
| <tt>NV..H.ZC</tt>
| Uses carry flag
|-
| <tt>CMPW YA, dp</tt>
| <tt>?</tt>
| <tt>5A</tt>
| 2
| 4
| <tt>N.....ZC</tt>
|
|-
| <tt>MUL YA</tt>
| <tt>?</tt>
| <tt>CF</tt>
| 1
| 9
| <tt>N.....Z.</tt>
| <tt>YA = Y * A</tt><br/>n/z flags based on Y register (high-byte) only
|-
| <tt>DIV YA, X</tt>
| <tt>?</tt>
| <tt>9E</tt>
| 1
| 12
| <tt>NV..H.Z.</tt>
| <tt>A = YA / X</tt>, <tt>Y = YA % X</tt><br/>Bit 8 of quotient is stored in the overflow (v) flag.<br/>Output only valid if quotient is &lt;= 511.<br/>n/z flags based on A register (bits 0-7 of quotient) only.
|-
| colspan=7 | . '''decimal adjust'''
|-
| <tt>DAA A</tt>
| <tt>?</tt>
| <tt>DF</tt>
| 1
| 3
| <tt>N.....ZC</tt>
| Apply carry/half-carry after BCD addition
|-
| <tt>DAS A</tt>
| <tt>?</tt>
| <tt>BE</tt>
| 1
| 3
| <tt>N.....ZC</tt>
| Apply carry/half-carry after BCD subtraction
|-
| colspan=7 | . '''branching'''
|-
| <tt>BRA rel</tt>
| <tt>BRA rel</tt>
| <tt>2F</tt>
| 2
| 4
| <tt>........</tt>
| Branch always
|-
| <tt>BEQ rel</tt>
| <tt>BEQ rel</tt>
| <tt>F0</tt>
| 2
| 2/4
| <tt>........</tt>
| Branch if Z=1
|-
| <tt>BNE rel</tt>
| <tt>BNE rel</tt>
| <tt>D0</tt>
| 2
| 2/4
| <tt>........</tt>
| Branch if Z=0
|-
| <tt>BCS rel</tt>
| <tt>BCS rel</tt>
| <tt>B0</tt>
| 2
| 2/4
| <tt>........</tt>
| Branch if C=1
|-
| <tt>BCC rel</tt>
| <tt>BCC rel</tt>
| <tt>90</tt>
| 2
| 2/4
| <tt>........</tt>
| Branch if C=0
|-
| <tt>BVS rel</tt>
| <tt>BVS rel</tt>
| <tt>70</tt>
| 2
| 2/4
| <tt>........</tt>
| Branch if V=1
|-
| <tt>BVC rel</tt>
| <tt>BVC rel</tt>
| <tt>50</tt>
| 2
| 2/4
| <tt>........</tt>
| Branch if V=0
|-
| <tt>BMI rel</tt>
| <tt>BMI rel</tt>
| <tt>30</tt>
| 2
| 2/4
| <tt>........</tt>
| Branch if N=1
|-
| <tt>BPL rel</tt>
| <tt>BPL rel</tt>
| <tt>10</tt>
| 2
| 2/4
| <tt>........</tt>
| Branch if N=0
|-
| <tt>BBS dp, bit, rel</tt>
| <tt>BBS bit, dp, rel</tt>
| <tt>x3</tt>
| 3
| 5/7
| <tt>........</tt>
| Branch if dp bit=1, x=(bit*2)
|-
| <tt>BBC dp, bit, rel</tt>
| <tt>BBR bit, dp, rel</tt>
| <tt>y3</tt>
| 3
| 5/7
| <tt>........</tt>
| Branch if dp bit=1, y=(bit*2)+1
|-
| <tt>CBNE dp, rel</tt>
| <tt>?</tt>
| <tt>2E</tt>
| 3
| 5/7
| <tt>........</tt>
| CMP A, dp then BNE
|-
| <tt>CBNE dp+X, rel</tt>
| <tt>?</tt>
| <tt>DE</tt>
| 3
| 6/8
| <tt>........</tt>
| CMP A, dp+X then BNE
|-
| <tt>DBNZ dp, rel</tt>
| <tt>?</tt>
| <tt>6E</tt>
| 3
| 5/7
| <tt>........</tt>
| DEC dp then BNE
|-
| <tt>DBNZ Y, rel</tt>
| <tt>?</tt>
| <tt>FE</tt>
| 2
| 4/6
| <tt>........</tt>
| DEC Y then BNE
|-
| <tt>JMP !abs</tt>
| <tt>JMP abs</tt>
| <tt>5F</tt>
| 3
| 3
| <tt>........</tt>
|
|-
| <tt>JMP [!abs+X]</tt>
| <tt>JMP (abs, X)</tt>
| <tt>1F</tt>
| 3
| 6
| <tt>........</tt>
|
|-
| colspan=7 | . '''subroutines'''
|-
| <tt>CALL !abs</tt>
| <tt>JSR abs</tt>
| <tt>3F</tt>
| 3
| 8
| <tt>........</tt>
|
|-
| <tt>PCALL up</tt>
| <tt>?</tt>
| <tt>4F</tt>
| 2
| 6
| <tt>........</tt>
| CALL $FF00 + up
|-
| <tt>TCALL n</tt>
| <tt>?</tt>
| <tt>n1</tt>
| 1
| 8
| <tt>........</tt>
| CALL [$FFDE-(2*n)]
|-
| <tt>BRK</tt>
| <tt>BRK</tt>
| <tt>0F</tt>
| 1
| 8
| <tt>...1.0..</tt>
|
|-
| <tt>RET</tt>
| <tt>RTS</tt>
| <tt>6F</tt>
| 1
| 5
| <tt>........</tt>
|
|-
| <tt>RETI</tt>
| <tt>RTI</tt>
| <tt>7F</tt>
| 1
| 6
| <tt>NVPBHIZC</tt>
|
|-
| colspan=7 | . '''stack'''
|-
| <tt>PUSH A</tt>
| <tt>PHA</tt>
| <tt>2D</tt>
| 1
| 4
| <tt>........</tt>
|
|-
| <tt>PUSH X</tt>
| <tt>PHX</tt>
| <tt>4D</tt>
| 1
| 4
| <tt>........</tt>
|
|-
| <tt>PUSH Y</tt>
| <tt>PHY</tt>
| <tt>6D</tt>
| 1
| 4
| <tt>........</tt>
|
|-
| <tt>PUSH PSW</tt>
| <tt>PHP</tt>
| <tt>0D</tt>
| 1
| 4
| <tt>........</tt>
|
|-
| <tt>POP A</tt>
| <tt>PLA</tt>
| <tt>AE</tt>
| 1
| 4
| <tt>........</tt>
|
|-
| <tt>POP X</tt>
| <tt>PLX</tt>
| <tt>CE</tt>
| 1
| 4
| <tt>........</tt>
|
|-
| <tt>POP Y</tt>
| <tt>PLY</tt>
| <tt>EE</tt>
| 1
| 4
| <tt>........</tt>
|
|-
| <tt>POP PSW</tt>
| <tt>PLP</tt>
| <tt>8E</tt>
| 1
| 4
| <tt>NVPBHIZC</tt>
|
|-
| colspan=7 | . '''memory bit operations'''
|-
| <tt>SET1 dp, bit</tt>
| <tt>SMB bit, dp</tt>
| <tt>x2</tt>
| 2
| 4
| <tt>........</tt>
| Set dp bit, x=(bit*2)
|-
| <tt>CLR1 dp, bit</tt>
| <tt>RMB bit, dp</tt>
| <tt>y2</tt>
| 2
| 4
| <tt>........</tt>
| Set dp bit, y=(bit*2)+1
|-
| <tt>TSET1 !abs</tt>
| <tt>TSB abs</tt>
| <tt>0E</tt>
| 3
| 6
| <tt>N.....Z.</tt>
| Test and set bits with A<br/>Equality test (<tt>A - old_value</tt>)
|-
| <tt>TCLR1 !abs</tt>
| <tt>TRB abs</tt>
| <tt>4E</tt>
| 3
| 6
| <tt>N.....Z.</tt>
| Test and clear bits with A<br/>Equality test (<tt>A - old_value</tt>)
|-
| <tt>AND1 C, abs, bit</tt>
| <tt>?</tt>
| <tt>4A</tt>
| 3
| 4
| <tt>.......C</tt>
| C &= [abs] bit
|-
| <tt>AND1 C, /abs, bit</tt>
| <tt>?</tt>
| <tt>6A</tt>
| 3
| 4
| <tt>.......C</tt>
| C &= !([abs] bit)
|-
| <tt>OR1 C, abs, bit</tt>
| <tt>?</tt>
| <tt>0A</tt>
| 3
| 5
| <tt>.......C</tt>
| C <nowiki>|</nowiki>= [abs] bit
|-
| <tt>OR1 C, /abs, bit</tt>
| <tt>?</tt>
| <tt>2A</tt>
| 3
| 5
| <tt>.......C</tt>
| C <nowiki>|</nowiki>= !([abs] bit)
|-
| <tt>EOR1 C, abs, bit</tt>
| <tt>?</tt>
| <tt>8A</tt>
| 3
| 5
| <tt>.......C</tt>
| C ^= [abs] bit
|-
| <tt>NOT1 abs, bit</tt>
| <tt>?</tt>
| <tt>EA</tt>
| 3
| 5
| <tt>........</tt>
| [abs] bit ^= 1
|-
| <tt>MOV1 C, abs, bit</tt>
| <tt>?</tt>
| <tt>AA</tt>
| 3
| 4
| <tt>.......C</tt>
| C = [abs] bit
|-
| <tt>MOV1 abs, bit, C</tt>
| <tt>?</tt>
| <tt>CA</tt>
| 3
| 6
| <tt>........</tt>
| [abs] bit = C
|-
| colspan=7 | . '''status flags'''
|-
| <tt>CLRC</tt>
| <tt>CLC</tt>
| <tt>60</tt>
| 1
| 2
| <tt>.......0</tt>
|
|-
| <tt>SETC</tt>
| <tt>SEC</tt>
| <tt>80</tt>
| 1
| 2
| <tt>.......1</tt>
|
|-
| <tt>NOTC</tt>
| <tt>?</tt>
| <tt>ED</tt>
| 1
| 3
| <tt>.......C</tt>
| C ^= 1
|-
| <tt>CLRV</tt>
| <tt>CLV</tt>
| <tt>E0</tt>
| 1
| 2
| <tt>.0..0...</tt>
| Clears V and H
|-
| <tt>CLRP</tt>
| <tt>?</tt>
| <tt>20</tt>
| 1
| 2
| <tt>..0.....</tt>
|
|-
| <tt>SETP</tt>
| <tt>?</tt>
| <tt>40</tt>
| 1
| 2
| <tt>..1.....</tt>
|
|-
| <tt>EI</tt>
| <tt>CLI</tt>
| <tt>A0</tt>
| 1
| 3
| <tt>......1.</tt>
|
|-
| <tt>DI</tt>
| <tt>SEI</tt>
| <tt>C0</tt>
| 1
| 3
| <tt>......0.</tt>
|
|-
| colspan=7 | . '''no-operation and halt'''
|-
| <tt>NOP</tt>
| <tt>NOP</tt>
| <tt>00</tt>
| 1
| 2
| <tt>........</tt>
|
|-
| <tt>SLEEP</tt>
| <tt>WAI</tt>
| <tt>EF</tt>
| 1
| 3
| <tt>........</tt>
|
|-
| <tt>STOP</tt>
| <tt>STP</tt>
| <tt>FF</tt>
| 1
| 2
| <tt>........</tt>
|
|}
|}
Instruction list:
* <tt>MOV</tt>
* <tt>ADC</tt> <tt>SBC</tt> <tt>CMP</tt>
* <tt>AND</tt> <tt>OR</tt> <tt>EOR</tt> <tt>ASL</tt> <tt>LSR</tt> <tt>ROL</tt> <tt>XCN</tt>
* <tt>INC</tt> <tt>DEC</tt>
* <tt>MOVW</tt> <tt>INCW</tt> <tt>DECW</tt> <tt>ADDW</tt> <tt>SUBW</tt> <tt>CMPW</tt> <tt>MUL</tt> <tt>DIV</tt>
* <tt>DAA</tt> <tt>DAS</tt>
* <tt>BRA</tt> <tt>BEQ</tt> <tt>BNE</tt> <tt>BCS</tt> <tt>BCC</tt> <tt>BVS</tt> <tt>BVC</tt> <tt>BMI</tt> <tt>BPL</tt> <tt>BBS</tt> <tt>BBC</tt> <tt>CBNE</tt> <tt>DBNZ</tt> <tt>JMP</tt>
* <tt>CALL</tt> <tt>PCALL</tt> <tt>TCALL</tt> <tt>BRK</tt> <tt>RET</tt> <tt>RETI</tt>
* <tt>PUSH</tt> <tt>POP</tt>
* <tt>SET1</tt> <tt>CLR1</tt> <tt>TSET1</tt> <tt>TCLR1</tt> <tt>AND1</tt> <tt>OR1</tt> <tt>EOR1</tt> <tt>NOT1</tt> <tt>MOV1</tt>
* <tt>CLRC</tt> <tt>SETC</tt> <tt>NOTC</tt> <tt>CLRV</tt> <tt>CLRP</tt> <tt>SETP</tt> <tt>EI</tt> <tt>DI</tt>
* <tt>NOP</tt> <tt>SLEEP</tt> <tt>STOP</tt>


== Links ==
== Links ==

Latest revision as of 17:16, 4 March 2024

The Sony SPC-700 CPU is part of the S-SMP sound processor of the SNES. It runs at 1.024 MHz, and behaves similarly to a 6502 with some extensions.

Architecture

The SPC-700 has a 16-bit address space, and a similar set of registers to the 6502.

Registers

  • A - 8-bit accumulator
  • X - 8-bit index
  • Y - 8-bit index
  • YA - 16-bit pair of A (lsb) and Y (msb).
  • PC - program counter
  • SP - stack pointer
  • PSW - program status word: NVPBHIZC
    • N - negative flag (high bit of result was set)
    • V - overflow flag (signed overflow indication)
    • P - direct page flag (moves the direct page to $0100 if set)
    • H - half-carry flag (carry between low and high nibble)
    • I - interrupt enable (unused: the S-SMP has no attached interrupts)
    • Z - zero flag (set if last result was zero)
    • C - carry flag

Addressing Modes

  • imm - 8-bit immediate value
  • dp - 8-bit direct page offset ($0000 + dp or $0100 + dp)
  • !abs - 16-bit absolute address
  • rel - relative offset in two's complement
  • (i) - direct-page relative index (P * $100 + i)
  • (i)+ - direct-page relative index with post-increment (i is incremented after read)
  • [addr]+i - indirect indexed (add index after 16-bit lookup)
  • [addr+i] - indexed indirect (add index before 16-bit lookup)

Differences from the 6502

Removed from SPC700

  • Decimal mode is missing; instead, DAA and DAS instructions which use the added half-carry flag are provided.
  • The indirect non-indexed variant of JMP.
  • The LDX abs, Y and LDY abs, X instructions.
  • The BIT instruction.
  • abs, X modes in read-modify-write instructions: INC, DEC, ASL, LSR, ROL, ROR. (The zp, X and abs modes are available).

New to SPC700

  • The direct page can be moved to $0100. (Rarely used.)
  • 16-bit operations, using either the direct page or the new 16-bit register YA:
    • MOVW, ADDW, SUBW, CMPW, INCW, DECW.
    • MUL, DIV: multiply/divide instructions.
  • CBNE, DBNZ: loop instructions.
  • PCALL, TCALL: abbreviated call instructions for the high page of memory.
  • SET1, NOT1, MOV1, AND1, OR1, EOR1: single-bit operations on the lower 8KB of memory.
  • XCN A: nibble exchange.

New addressing modes:

  • Load/store, arithmetic and boolean operations have added the following modes:
    • Direct page <- Immediate: MOV dp, #imm
    • Direct page <- Direct page: AND dp, dp
    • A <- Direct page pointer in X: OR A, (X)
    • Direct page pointer in X <- Direct page pointer in Y: EOR (X), (Y)
  • Load/store operations have added these additional modes:
    • Direct page pointer in X, post-increment: MOV (X)+

Note that some features, despite not being available in the original 6502, have been previously introduced by the 65C02:

  • BBC, BBS: branch on an individual bit set/clear in direct page locations.
  • BRA: branch always.
  • INC, DEC for the accumulator.
  • RMB, SMB: set/clear an individual bit in direct page locations.
  • The indirect indexed variant of JMP.
  • The ability to directly push and pop X and Y.

Changed in SPC700

  • Interrupt status flag is enable, not disable. (Not important for SNES: there is no IRQ.)
  • The cycle timings of many instructions are slightly different.
  • POP instructions do not modify flags (except POP PSW).
  • CALL places the address of the next instruction on the stack, rather than a pre-increment (-1) address like the 6502. RET similarly does not have a post-increment for the popped address.
  • TSET1 and TCLR1 don't work like TSB and TRB on the 65C02: instead of using a bit test to set Z, the N/Z flags are set using an equality test.

Instructions

Official instruction names and syntax for SPC-700 instruction were provided by Sony. However, because of its architectural similarity to 6502, some prefer to rename and remap them using a 6502 style syntax. Both are provided here.

Sony instruction convention puts the destination on the left, source on the right (Intel syntax).

Cycles in this table are 1.024 MHz CPU cycles. Each one is equal to 2 clocks of the 2.048 MHz S-SMP.

SPC-700 Instruction Set
Instruction 6502-Style Opcode Bytes Cycles Flags Notes
. 8-bit move memory to register
MOV A, #imm LDA #imm E8 2 2 N.....Z.
MOV A, (X) ? E6 1 3 N.....Z.
MOV A, (X)+ ? BF 1 4 N.....Z. X++ after read
MOV A, dp LDA dp E4 2 3 N.....Z.
MOV A, dp+X LDA dp, X F4 2 4 N.....Z.
MOV A, !abs LDA abs E5 3 4 N.....Z.
MOV A, !abs+X LDA abs, X F5 3 5 N.....Z.
MOV A, !abs+Y LDA abs, Y F6 3 5 N.....Z.
MOV A, [dp+X] LDA (dp, X) E7 2 6 N.....Z.
MOV A, [dp]+Y LDA (dp), Y F7 2 6 N.....Z.
MOV X, #imm LDX #imm CD 2 2 N.....Z.
MOV X, dp LDX dp F8 2 3 N.....Z.
MOV X, dp+Y LDX dp, Y F9 2 4 N.....Z.
MOV X, !abs LDX abs E9 3 4 N.....Z.
MOV Y, #imm LDY #imm 8D 2 2 N.....Z.
MOV Y, dp LDY dp EB 2 3 N.....Z.
MOV Y, dp+X LDY dp, X FB 2 4 N.....Z.
MOV Y, !abs LDY abs EC 3 4 N.....Z.
. 8-bit move register to memory
MOV (X), A ? C6 1 4 ........
MOV (X)+, A ? AF 1 4 ........ X++ after read
MOV dp, A STA dp C4 2 4 ........
MOV dp+X, A STA dp, X D4 2 5 ........
MOV !abs, A STA abs C5 3 5 ........
MOV !abs+X, A STA abs, X D5 3 6 ........
MOV !abs+Y, A STA abs, Y D6 3 6 ........
MOV [dp+X], A STA (dp, X) C7 2 7 ........
MOV [dp]+Y, A STA (dp), Y D7 2 7 ........
MOV dp, X STX dp D8 2 4 ........
MOV dp+Y, X STX dp, Y D9 2 5 ........
MOV !abs, X STX abs C9 3 5 ........
MOV dp, Y STY dp CB 2 4 ........
MOV dp+X, Y STY dp, X DB 2 5 ........
MOV !abs, Y STY abs CC 3 5 ........
. 8-bit move register to register / special direct page moves
MOV A, X TXA 7D 1 2 N.....Z.
MOV A, Y TYA DD 1 2 N.....Z.
MOV X, A TAX 5D 1 2 N.....Z.
MOV Y, A TAY FD 1 2 N.....Z.
MOV X, SP TSX 9D 1 2 N.....Z.
MOV SP, X TXS BD 1 2 ........
MOV dp, dp ? FA 3 5 ........
MOV dp, #imm ? 8F 3 5 ........
. 8-bit arithmetic
ADC A, #imm ADC #imm 88 2 2 NV..H.ZC
ADC A, (X) ? 86 1 3 NV..H.ZC
ADC A, dp ADC dp 84 2 3 NV..H.ZC
ADC A, dp+X ADC dp, X 94 2 4 NV..H.ZC
ADC A, !abs ADC abs 85 3 4 NV..H.ZC
ADC A, !abs+X ADC abs, X 95 3 5 NV..H.ZC
ADC A, !abs+Y ADC abs, Y 96 3 5 NV..H.ZC
ADC A, [dp+X] ADC (dp, X) 87 2 6 NV..H.ZC
ADC A, [dp]+Y ADC (dp), Y 97 2 6 NV..H.ZC
ADC (X), (Y) ? 99 1 5 NV..H.ZC
ADC dp, dp ? 89 3 6 NV..H.ZC
ADC dp, #imm ? 98 3 5 NV..H.ZC
SBC A, #imm SBC #imm A8 2 2 NV..H.ZC
SBC A, (X) ? A6 1 3 NV..H.ZC
SBC A, dp SBC dp A4 2 3 NV..H.ZC
SBC A, dp+X SBC dp, X B4 2 4 NV..H.ZC
SBC A, !abs SBC abs A5 3 4 NV..H.ZC
SBC A, !abs+X SBC abs, X B5 3 5 NV..H.ZC
SBC A, !abs+Y SBC abs, Y B6 3 5 NV..H.ZC
SBC A, [dp+X] SBC (dp, X) A7 2 6 NV..H.ZC
SBC A, [dp]+Y SBC (dp), Y B7 2 6 NV..H.ZC
SBC (X), (Y) ? B9 1 5 NV..H.ZC
SBC dp, dp ? A9 3 6 NV..H.ZC
SBC dp, #imm ? B8 3 5 NV..H.ZC
CMP A, #imm CMP #imm 68 2 2 N.....ZC
CMP A, (X) ? 66 1 3 N.....ZC
CMP A, dp CMP dp 64 2 3 N.....ZC
CMP A, dp+X CMP dp, X 74 2 4 N.....ZC
CMP A, !abs CMP abs 65 3 4 N.....ZC
CMP A, !abs+X CMP abs, X 75 3 5 N.....ZC
CMP A, !abs+Y CMP abs, Y 76 3 5 N.....ZC
CMP A, [dp+X] CMP (dp, X) 67 2 6 N.....ZC
CMP A, [dp]+Y CMP (dp), Y 77 2 6 N.....ZC
CMP (X), (Y) ? 79 1 5 N.....ZC
CMP dp, dp ? 69 3 6 N.....ZC
CMP dp, #imm ? 78 3 5 N.....ZC
CMP X, #imm CPX #imm C8 2 2 N.....ZC
CMP X, dp CPX dp 3E 2 3 N.....ZC
CMP X, !abs CPX abs 1E 3 4 N.....ZC
CMP Y, #imm CPY #imm AD 2 2 N.....ZC
CMP Y, dp CPY dp 7E 2 3 N.....ZC
CMP Y, !abs CPY abs 5E 3 4 N.....ZC
. 8-bit boolean logic
AND A, #imm AND #imm 28 2 2 N.....Z.
AND A, (X) ? 26 1 3 N.....Z.
AND A, dp AND dp 24 2 3 N.....Z.
AND A, dp+X AND dp, X 34 2 4 N.....Z.
AND A, !abs AND abs 25 3 4 N.....Z.
AND A, !abs+X AND abs, X 35 3 5 N.....Z.
AND A, !abs+Y AND abs, Y 36 3 5 N.....Z.
AND A, [dp+X] AND (dp, X) 27 2 6 N.....Z.
AND A, [dp]+Y AND (dp), Y 37 2 6 N.....Z.
AND (X), (Y) ? 39 1 5 N.....Z.
AND dp, dp ? 29 3 6 N.....Z.
AND dp, #imm ? 38 3 5 N.....Z.
OR A, #imm ORA #imm 08 2 2 N.....Z.
OR A, (X) ? 06 1 3 N.....Z.
OR A, dp ORA dp 04 2 3 N.....Z.
OR A, dp+X ORA dp, X 14 2 4 N.....Z.
OR A, !abs ORA abs 05 3 4 N.....Z.
OR A, !abs+X ORA abs, X 15 3 5 N.....Z.
OR A, !abs+Y ORA abs, Y 16 3 5 N.....Z.
OR A, [dp+X] ORA (dp, X) 07 2 6 N.....Z.
OR A, [dp]+Y ORA (dp), Y 17 2 6 N.....Z.
OR (X), (Y) ? 19 1 5 N.....Z.
OR dp, dp ? 09 3 6 N.....Z.
OR dp, #imm ? 18 3 5 N.....Z.
EOR A, #imm EOR #imm 48 2 2 N.....Z.
EOR A, (X) ? 46 1 3 N.....Z.
EOR A, dp EOR dp 44 2 3 N.....Z.
EOR A, dp+X EOR dp, X 54 2 4 N.....Z.
EOR A, !abs EOR abs 45 3 4 N.....Z.
EOR A, !abs+X EOR abs, X 55 3 5 N.....Z.
EOR A, !abs+Y EOR abs, Y 56 3 5 N.....Z.
EOR A, [dp+X] EOR (dp, X) 47 2 6 N.....Z.
EOR A, [dp]+Y EOR (dp), Y 57 2 6 N.....Z.
EOR (X), (Y) ? 59 1 5 N.....Z.
EOR dp, dp ? 49 3 6 N.....Z.
EOR dp, #imm ? 58 3 5 N.....Z.
. 8-bit increment / decrement
INC A INC BC 1 2 N.....Z.
INC dp INC dp AB 2 4 N.....Z.
INC dp+X INC dp, X BB 2 5 N.....Z.
INC !abs INC abs AC 3 5 N.....Z.
INC X INX 3D 1 2 N.....Z.
INC Y INY FC 1 2 N.....Z.
DEC A DEC 9C 1 2 N.....Z.
DEC dp DEC dp 8B 2 4 N.....Z.
DEC dp+X DEC dp, X 9B 2 5 N.....Z.
DEC !abs DEC abs 8C 3 5 N.....Z.
DEC X DEX 1D 1 2 N.....Z.
DEC Y DEY DC 1 2 N.....Z.
. 8-bit shift / rotation
ASL A ASL 1C 1 2 N.....ZC
ASL dp ASL dp 0B 2 4 N.....ZC
ASL dp+X ASL dp, X 1B 2 5 N.....ZC
ASL !abs ASL abs 0C 3 5 N.....ZC
LSR A LSR 5C 1 2 N.....ZC
LSR dp LSR dp 4B 2 4 N.....ZC
LSR dp+X LSR dp, X 5B 2 5 N.....ZC
LSR !abs LSR abs 4C 3 5 N.....ZC
ROL A ROL 3C 1 2 N.....ZC
ROL dp ROL dp 2B 2 4 N.....ZC
ROL dp+X ROL dp, X 3B 2 5 N.....ZC
ROL !abs ROL abs 2C 3 5 N.....ZC
ROR A ROR 7C 1 2 N.....ZC
ROR dp ROR dp 6B 2 4 N.....ZC
ROR dp+X ROR dp, X 7B 2 5 N.....ZC
ROR !abs ROR abs 6C 3 5 N.....ZC
XCN A ? 9F 1 5 N.....Z. Exchange nibbles of A
. 16-bit operations
MOVW YA, dp ? BA 2 5 N.....Z.
MOVW dp, YA ? DA 2 4 ........
INCW dp ? 3A 2 6 N.....Z.
DECW dp ? 1A 2 6 N.....Z.
ADDW YA, dp ? 7A 2 5 NV..H.ZC Uses carry flag
SUBW YA, dp ? 9A 2 5 NV..H.ZC Uses carry flag
CMPW YA, dp ? 5A 2 4 N.....ZC
MUL YA ? CF 1 9 N.....Z. YA = Y * A
n/z flags based on Y register (high-byte) only
DIV YA, X ? 9E 1 12 NV..H.Z. A = YA / X, Y = YA % X
Bit 8 of quotient is stored in the overflow (v) flag.
Output only valid if quotient is <= 511.
n/z flags based on A register (bits 0-7 of quotient) only.
. decimal adjust
DAA A ? DF 1 3 N.....ZC Apply carry/half-carry after BCD addition
DAS A ? BE 1 3 N.....ZC Apply carry/half-carry after BCD subtraction
. branching
BRA rel BRA rel 2F 2 4 ........ Branch always
BEQ rel BEQ rel F0 2 2/4 ........ Branch if Z=1
BNE rel BNE rel D0 2 2/4 ........ Branch if Z=0
BCS rel BCS rel B0 2 2/4 ........ Branch if C=1
BCC rel BCC rel 90 2 2/4 ........ Branch if C=0
BVS rel BVS rel 70 2 2/4 ........ Branch if V=1
BVC rel BVC rel 50 2 2/4 ........ Branch if V=0
BMI rel BMI rel 30 2 2/4 ........ Branch if N=1
BPL rel BPL rel 10 2 2/4 ........ Branch if N=0
BBS dp, bit, rel BBS bit, dp, rel x3 3 5/7 ........ Branch if dp bit=1, x=(bit*2)
BBC dp, bit, rel BBR bit, dp, rel y3 3 5/7 ........ Branch if dp bit=1, y=(bit*2)+1
CBNE dp, rel ? 2E 3 5/7 ........ CMP A, dp then BNE
CBNE dp+X, rel ? DE 3 6/8 ........ CMP A, dp+X then BNE
DBNZ dp, rel ? 6E 3 5/7 ........ DEC dp then BNE
DBNZ Y, rel ? FE 2 4/6 ........ DEC Y then BNE
JMP !abs JMP abs 5F 3 3 ........
JMP [!abs+X] JMP (abs, X) 1F 3 6 ........
. subroutines
CALL !abs JSR abs 3F 3 8 ........
PCALL up ? 4F 2 6 ........ CALL $FF00 + up
TCALL n ? n1 1 8 ........ CALL [$FFDE-(2*n)]
BRK BRK 0F 1 8 ...1.0..
RET RTS 6F 1 5 ........
RETI RTI 7F 1 6 NVPBHIZC
. stack
PUSH A PHA 2D 1 4 ........
PUSH X PHX 4D 1 4 ........
PUSH Y PHY 6D 1 4 ........
PUSH PSW PHP 0D 1 4 ........
POP A PLA AE 1 4 ........
POP X PLX CE 1 4 ........
POP Y PLY EE 1 4 ........
POP PSW PLP 8E 1 4 NVPBHIZC
. memory bit operations
SET1 dp, bit SMB bit, dp x2 2 4 ........ Set dp bit, x=(bit*2)
CLR1 dp, bit RMB bit, dp y2 2 4 ........ Set dp bit, y=(bit*2)+1
TSET1 !abs TSB abs 0E 3 6 N.....Z. Test and set bits with A
Equality test (A - old_value)
TCLR1 !abs TRB abs 4E 3 6 N.....Z. Test and clear bits with A
Equality test (A - old_value)
AND1 C, abs, bit ? 4A 3 4 .......C C &= [abs] bit
AND1 C, /abs, bit ? 6A 3 4 .......C C &= !([abs] bit)
OR1 C, abs, bit ? 0A 3 5 .......C C |= [abs] bit
OR1 C, /abs, bit ? 2A 3 5 .......C C |= !([abs] bit)
EOR1 C, abs, bit ? 8A 3 5 .......C C ^= [abs] bit
NOT1 abs, bit ? EA 3 5 ........ [abs] bit ^= 1
MOV1 C, abs, bit ? AA 3 4 .......C C = [abs] bit
MOV1 abs, bit, C ? CA 3 6 ........ [abs] bit = C
. status flags
CLRC CLC 60 1 2 .......0
SETC SEC 80 1 2 .......1
NOTC ? ED 1 3 .......C C ^= 1
CLRV CLV E0 1 2 .0..0... Clears V and H
CLRP ? 20 1 2 ..0.....
SETP ? 40 1 2 ..1.....
EI CLI A0 1 3 ......1.
DI SEI C0 1 3 ......0.
. no-operation and halt
NOP NOP 00 1 2 ........
SLEEP WAI EF 1 3 ........
STOP STP FF 1 2 ........

Instruction list:

  • MOV
  • ADC SBC CMP
  • AND OR EOR ASL LSR ROL XCN
  • INC DEC
  • MOVW INCW DECW ADDW SUBW CMPW MUL DIV
  • DAA DAS
  • BRA BEQ BNE BCS BCC BVS BVC BMI BPL BBS BBC CBNE DBNZ JMP
  • CALL PCALL TCALL BRK RET RETI
  • PUSH POP
  • SET1 CLR1 TSET1 TCLR1 AND1 OR1 EOR1 NOT1 MOV1
  • CLRC SETC NOTC CLRV CLRP SETP EI DI
  • NOP SLEEP STOP

Links