SPC-700 instruction set: Difference between revisions

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* !abs - 16-bit absolute address
* !abs - 16-bit absolute address
* rel - relative offset in two's complement
* rel - relative offset in two's complement
* (addr) - indirect
* (i) - direct-page relative index (P * $100 + i)
* (addr)+i - indirect indexed (add index after lookup)
* (i)+ - direct-page relative index with post-increment (i is incremented after read)
* [addr]+i - indirect indexed (add index after lookup)
* [addr+i] - indexed indirect (add index before lookup)
* [addr+i] - indexed indirect (add index before lookup)



Revision as of 04:23, 7 October 2022

The Sony SPC-700 CPU is part of the S-SMP sound processor of the SNES. It runs at 2.048 MHz, and behaves similarly to a 6502 at 1.024 MHz with some extensions.

Architecture

The SPC-700 has a 16-bit address space, and a similar set of registers to the 6502.

Registers

  • A - 8-bit accumulator
  • X - 8-bit index
  • Y - 8-bit index
  • YA - 16-bit pair of A (lsb) and Y (msb).
  • PC - program counter
  • SP - stack pointer
  • PSW - program status word: NVPBHIZC
    • N - negative flag (high bit of result was set)
    • V - overflow flag (signed overflow indication)
    • P - direct page flag (moves the direct page to $0100 if set)
    • H - half carry flag (carry between low and high nibble)
    • I - interrupt disable (unused: the S-SMP has no attached interrupts)
    • Z - zero flag (set if last result was zero)
    • C - carry flag

Differences from the 6502:

  • A 16-bit combined YA register is available for some operations.
  • The direct page can be moved to $0100. (Rarely used.)
  • A half carry flag that is useful for nibble operations.
  • No decimal mode.

Addressing Modes

  • imm - 8-bit immediate value
  • dp - 8-bit direct page offset ($0000+dp or $01000+dp)
  • !abs - 16-bit absolute address
  • rel - relative offset in two's complement
  • (i) - direct-page relative index (P * $100 + i)
  • (i)+ - direct-page relative index with post-increment (i is incremented after read)
  • [addr]+i - indirect indexed (add index after lookup)
  • [addr+i] - indexed indirect (add index before lookup)

Instructions

Official instruction names and syntax for SPC-700 instruction were provided by Sony. However, because of its architectural similarity to 6502, some prefer to rename and remap them using a 6502 style syntax. Both are provided here.

Cycles in this table are 1.024 MHz CPU cycles. Each one is equal to 2 clocks of the 2.048 Mhz S-SMP.

SPC-700 Instruction Set
Instruction 6502-Style Opcode Bytes Cycles Flags Notes
8-bit move to register
MOV A, #imm LDA #imm E8 2 2 N......Z
MOV A, (X) ? E6 1 3 N......Z Loads from (P * $100) + X
MOV A, (X)+ ? BF 1 4 N......Z X is incremented after the read
MOV A, dp LDA zp E4 2 3 N......Z
MOV A, dp+X LDA zp, X F4 2 4 N......Z
MOV A, !abs LDA abs E5 3 4 N......Z
MOV A, !abs+X LDA abs, X F5 3 5 N......Z
MOV A, !abs+Y LDA abs, Y F6 3 5 N......Z
MOV A, [dp+X] LDA (zp, X) E7 2 6 N......Z
MOV A, [dp]+Y LDA (dp), Y F7 2 6 N......Z
MOV X, #imm LDX #imm CD 2 2 N......Z
MOV X, dp LDX zp F8 2 3 N......Z
MOV X, dp+Y LDX zp, Y F9 2 4 N......Z
MOV X, !abs LDX abs E9 3 4 N......Z
MOV Y, #imm LDY #imm 8D 2 2 N......Z
MOV Y, dp LDY zp EB 2 3 N......Z
MOV Y, dp+X LDY zp, X FB 2 4 N......Z
MOV Y, !abs LDY abs EC 3 4 N......Z
8-bit move to memory
TODO

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