User contributions for Fiskbit
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8 February 2024
- 22:1222:12, 8 February 2024 diff hist +2 m PPU registers →CGDATAREAD - CGRAM data read ($213B read twice): Formatting. current
23 January 2024
- 06:3606:36, 23 January 2024 diff hist −1 m ROM header →Non Power-of-2 ROM Size: but -> so
- 06:3406:34, 23 January 2024 diff hist −8 ROM header →Checksum: Minor edits for flow. Removes 'to save size' (there are arguably multiple reasons why ROMs don't contain data duplicates).
- 05:0305:03, 23 January 2024 diff hist +160 m ROM header →Checksum: Mentions that for most non-power-of-2 ROMs, resizing is just duplicating the last third.
- 04:2504:25, 23 January 2024 diff hist +252 ROM header →Checksum: Fixes checksum to use bytes instead of words. Clarifies comment about adding a value and its complement. Rewords things to maybe be a bit clearer and not bury the lede. Minor formatting changes.
12 January 2024
- 10:4710:47, 12 January 2024 diff hist 0 m Controller connector Fixes JOY register typo. current
- 09:3909:39, 12 January 2024 diff hist +344 Controller connector Reformats the pinout to match our typical layout (names and directions in the diagram). De-densifies the information. Adds more detailed signal descriptions.
11 January 2024
- 21:0521:05, 11 January 2024 diff hist −16 Open bus 5A22 register reads are not visible externally. (e.g. SD2SNES requires code hooks to get joypad state.) current
- 16:1716:17, 11 January 2024 diff hist +1,863 Open bus Makes this page more accurate and detailed. Adds decay time reference.
10 January 2024
- 11:2711:27, 10 January 2024 diff hist +4 m PPU registers Explicitly notes that SLHV open bus is CPU open bus. Makes 'if' formatting on register access consistently use colon instead of comma.
19 October 2023
- 02:3902:39, 19 October 2023 diff hist +68 PPU pinout →Signal descriptions: EXTLATCH apparently connects to joypad 2 D1 on the Sharp SF-1 Super Famicom TV. Reported by l_oliveira. current
23 August 2023
- 09:1509:15, 23 August 2023 diff hist +12 N MediaWiki:Mainpage Point to the new main page name. current
- 09:1409:14, 23 August 2023 diff hist +26 N Main Page Fiskbit moved page Main Page to SNESdev Wiki: Rename main page to match wiki name. current Tag: New redirect
- 09:1409:14, 23 August 2023 diff hist 0 m SNESdev Wiki Fiskbit moved page Main Page to SNESdev Wiki: Rename main page to match wiki name. current
21 March 2023
- 10:0910:09, 21 March 2023 diff hist +18 m Reading and writing PPU memory Adds references category to separate out the references.
24 February 2023
- 16:3216:32, 24 February 2023 diff hist +287 N MediaWiki:Loginprompt Adds log-in prompt explaining how to register an account. current
3 June 2022
- 00:5800:58, 3 June 2022 diff hist 0 m CPU pinout Adds missing CPU prefix on A23. current
1 June 2022
- 04:1704:17, 1 June 2022 diff hist +599 Backgrounds Adds padding to priorities in BG mode table.
- 04:1304:13, 1 June 2022 diff hist +25 Sprites Notes which direction the priorities go in.
31 May 2022
- 11:5611:56, 31 May 2022 diff hist +9 m Errata More clarity on vblank NMI behavior.
- 11:5511:55, 31 May 2022 diff hist +249 Errata →Video: Further explains the behavior where enabling NMIs during vblank triggers an immediate NMI.
- 11:3211:32, 31 May 2022 diff hist +2 m Errata →References: Uses : to indent non-automated references to match automated ones.
30 May 2022
- 06:1106:11, 30 May 2022 diff hist 0 OAM layout Fixes sprite indices 0-15.
29 May 2022
- 00:3400:34, 29 May 2022 diff hist −3 MediaWiki:Sidebar Changes the SNES Discord link to make it more clear it's not run by NESdev staff. (Sidebar size limits prevent longer, more descriptive links here without ugly wrapping.) current
28 May 2022
- 08:2908:29, 28 May 2022 diff hist +2 m Mouse →References: Uses : to match indentation of automated references.
26 May 2022
- 07:4107:41, 26 May 2022 diff hist +856 WRAM pinout Names for connected signals, more signal descriptions, and corrections. current
- 04:4204:42, 26 May 2022 diff hist −2 m Tilemaps →Mode 7: Fix formatting.
- 04:3504:35, 26 May 2022 diff hist −2 m Tiles →8bpp Direct Color: Changes bit diagram so it doesn't suggest involvement of unrelated bits.
- 03:5203:52, 26 May 2022 diff hist +8 m Timing JOYSERn link formatting.
- 01:2701:27, 26 May 2022 diff hist +18 SNESdev Wiki →General: Adds CPU vectors link.
- 01:2401:24, 26 May 2022 diff hist +54 ROM header Adds interrupts back to the table as a single link to CPU vectors page.
- 01:2201:22, 26 May 2022 diff hist +16 CPU vectors Puts empty slots and ABORT into the tables.
- 01:0301:03, 26 May 2022 diff hist +26 ROM header Adds link to CPU vectors page.
- 01:0101:01, 26 May 2022 diff hist −722 ROM header Moves vectors to 'CPU vectors' page and adds $ prefix to addresses.
- 00:5600:56, 26 May 2022 diff hist +1,088 N CPU vectors Adds CPU vector page.
25 May 2022
- 23:3723:37, 25 May 2022 diff hist +72 Standard controller Notes the read behavior past first 16 reads.
- 23:3523:35, 25 May 2022 diff hist 0 m PPU registers →OAMADDL, OAMADDH - OAM word address ($2102, $2103 write): Fixes register address typo.
- 23:1623:16, 25 May 2022 diff hist −471 SNESdev Wiki Remove MediaWiki links that aren't relevant to standard contributors.
- 23:1423:14, 25 May 2022 diff hist +18 SNESdev Wiki →Pinouts: Adds WRAM pinout link.
- 23:1423:14, 25 May 2022 diff hist 0 m CPU pinout →Pinout: Minor formatting fix.
- 23:1323:13, 25 May 2022 diff hist 0 m PPU pinout →Pinout: Minor formatting fix.
- 23:1323:13, 25 May 2022 diff hist +2,454 N WRAM pinout Adds S-WRAM pinout.
- 09:3009:30, 25 May 2022 diff hist +466 MMIO registers →NMITIMEN - Interrupts and Joypad reading ($4200 write): Adds NMI details. Mentions the slight delay before auto-read starts. Improves auto-read description.
- 08:1208:12, 25 May 2022 diff hist +106 DMA registers Clarifies the DMA RAM copy limitation.
- 07:2807:28, 25 May 2022 diff hist +125 DMA registers Adds CPU and peripheral bus names to the intro. Elaborates a bit on what DMA is doing to explain why transfers must be cross-bus.
- 07:0607:06, 25 May 2022 diff hist −18 m Memory map Uses consistent, unambiguous units (KiB and MiB).
- 06:0906:09, 25 May 2022 diff hist +1 m DMA registers →NLTRn - HDMA Line-Counter ($43nA read/write) (n = 0..7): Adds missing n suffix to NLTR.
- 06:0806:08, 25 May 2022 diff hist 0 m MMIO register table/DMA Fixes register name: NTRL -> NLTR.
- 06:0806:08, 25 May 2022 diff hist 0 m DMA registers Fixes register name: NTRL -> NLTR.
- 06:0706:07, 25 May 2022 diff hist +400 DMA registers Adds power-on and reset info for each register.
24 May 2022
- 11:5911:59, 24 May 2022 diff hist +11 m DMA registers Notes n range in table.
- 11:5811:58, 24 May 2022 diff hist +1 m MMIO register table/MMIO Minor formatting changes for consistency.
23 May 2022
- 16:4016:40, 23 May 2022 diff hist −1 m MMIO registers Typo.
- 16:4016:40, 23 May 2022 diff hist +45 m MMIO registers Links to Division page. Minor reformatting.
- 16:0316:03, 23 May 2022 diff hist −89 m MMIO registers There are no 8x2 registers here.
- 15:2715:27, 23 May 2022 diff hist +127 m MMIO registers Adds back in accidentally-dropped sentence.
- 15:2515:25, 23 May 2022 diff hist +4,126 MMIO registers Adds register summary table, adds links to PPU and DMA register pages, and change some bit letters.
- 13:4613:46, 23 May 2022 diff hist +1,173 MMIO registers Adds fastROM enable, power-on and reset values, and more APU register and math register details.
- 12:3212:32, 23 May 2022 diff hist +1,528 MMIO registers Adds APU and S-WRAM registers.
22 May 2022
- 23:4323:43, 22 May 2022 diff hist +1 SNESdev Wiki Fixes MMIO registers link.
- 22:4722:47, 22 May 2022 diff hist +1,473 MMIO registers Adds math registers.
- 22:2522:25, 22 May 2022 diff hist 0 PPU registers Changes counter bit letters from X and Y to H and V.
- 22:2022:20, 22 May 2022 diff hist +6 m PPU registers Make signed descriptors consistent with rest of the page.
- 22:1822:18, 22 May 2022 diff hist +42 PPU registers Add signed descriptor to multiplication bit definitions.
- 21:5621:56, 22 May 2022 diff hist +6 m Controller reading Fixes register links.
- 21:5521:55, 22 May 2022 diff hist 0 m MMIO registers Fiskbit moved page CPU registers to MMIO registers without leaving a redirect: Concluded after discussion that 'CPU registers' is both too narrow and somewhat misleading.
- 19:3319:33, 22 May 2022 diff hist +106 MMIO registers Auto-read description improvement.
- 19:2619:26, 22 May 2022 diff hist +53 MMIO registers Clarity improvements.
- 18:2318:23, 22 May 2022 diff hist +314 MMIO registers More precision regarding joypad bits.
- 17:3917:39, 22 May 2022 diff hist +3,695 MMIO registers Adds joypad registers.
- 16:2916:29, 22 May 2022 diff hist +86 m MMIO registers 16-bit register formatting.
- 16:1316:13, 22 May 2022 diff hist 0 m MMIO registers Formatting improvements.
- 16:1116:11, 22 May 2022 diff hist +2,197 MMIO registers Adds interrupt-related CPU registers.
19 May 2022
- 18:2318:23, 19 May 2022 diff hist −13 m PPU pinout Removes duplicate section header.
16 May 2022
- 20:2020:20, 16 May 2022 diff hist +71 m PPU registers Expands gaps between bytes in register definitions to 3 characters (enough to support 2-digit bit names on both sides).
- 19:3519:35, 16 May 2022 diff hist +300 m DMA registers Uses fixed-width, non-wrapping text for target addresses.
- 18:0218:02, 16 May 2022 diff hist 0 m PPU registers Corrects TS register address.
- 17:5517:55, 16 May 2022 diff hist +23 PPU registers Changes register summary type field to be more mobile-friendly. Adds types for each definition of a register (to more clearly distinguish W8 from W16).
- 16:4716:47, 16 May 2022 diff hist +584 PPU registers Changes register summary table formatting to match those on the NESdev wiki. Prevents wrapping between nybbles of individual bytes. Adds bit letters after each named item. Breaks out BG1 and M7 scroll register bit definitions because they're separate registers at the same address.
- 05:2005:20, 16 May 2022 diff hist −20 m Offset-per-tile Minor clarity improvements (hopefully).
- 04:4504:45, 16 May 2022 diff hist +24 m Offset-per-tile Minor formatting changes.
13 May 2022
- 17:2517:25, 13 May 2022 diff hist +209 DMA registers Some clarity improvements. (Using n with a range instead of x for registers to make it clear there are 8 unique registers of each type, not 16 and not with any mirroring. Using x for readable unused bit and specifying it's unused, not open bus. Trying to make even more clear that the multi-address unused byte is just one byte at both addresses. Improving the pattern table.)
- 16:5716:57, 13 May 2022 diff hist −123 PPU registers Merges low and high byte registers into combined definitions. Fixes on-write description for VMDATAxREAD
9 May 2022
- 04:4704:47, 9 May 2022 diff hist +78 PPU registers Explicitly notes which registers require 2 accesses.
8 May 2022
- 09:5809:58, 8 May 2022 diff hist +47 PPU registers Some minor formatting changes and consistent, unambiguous units. Formatting is in flux at these early stages and I'd love feedback, particularly as we add more content and see what does or doesn't work well. (Also, thank you so much for contributing! I actually found this to be one of the more-confusing registers while building this page.)
6 May 2022
- 15:4715:47, 6 May 2022 diff hist +1,753 PPU registers Adds OAM registers.
- 07:1407:14, 6 May 2022 diff hist +239 N MediaWiki:Sidebar Updates the sidebar.
- 05:4605:46, 6 May 2022 diff hist +19 PPU registers Another attempt at clearly explaining mode 7 tilemap boundary behavior.
- 05:2405:24, 6 May 2022 diff hist 0 m PPU registers Fixes COLDATA address.
- 05:2105:21, 6 May 2022 diff hist +598 PPU registers VRAM latching behavior.
- 04:4604:46, 6 May 2022 diff hist +78 PPU registers Further information on counter_latch behavior.
- 04:1204:12, 6 May 2022 diff hist +813 PPU registers Adds counter latching information (partly speculative). Existing documentation around this latching is incomplete and misleading. Also adds CGRAM latching information.
- 04:0604:06, 6 May 2022 diff hist +46 PPU pinout In order to explain counter latching behavior, EXTLATCH needs to be active low, not high.
- 00:5800:58, 6 May 2022 diff hist +21 PPU registers Mode 7 clarification. Formatting fixes.
- 00:3400:34, 6 May 2022 diff hist +1,038 PPU registers Corrections and clarifications around overlapping registers and value latches.
5 May 2022
- 11:2411:24, 5 May 2022 diff hist +2 m PPU registers Naming improvement.
- 11:2211:22, 5 May 2022 diff hist +76 PPU registers →STAT78 - PPU2 status flag and version ($213F read): Notes external latch flag read side effect and NTSC/PAL mode pin.
- 11:1311:13, 5 May 2022 diff hist +1,841 PPU registers Adds multiplication, counters, status registers.
- 10:0210:02, 5 May 2022 diff hist +2,456 PPU registers Adds scroll and mode 7 registers.
4 May 2022
- 09:0609:06, 4 May 2022 diff hist +2,212 PPU registers Adds VRAM and CGRAM registers.
- 04:3304:33, 4 May 2022 diff hist +2,337 PPU registers More registers. Some reformatting and formatting fixes.
27 April 2022
- 22:5622:56, 27 April 2022 diff hist −6 m APU pinout No need to mention CS and /CS in connector pinout.
- 12:5712:57, 27 April 2022 diff hist +15 APU pinout Improvements to sound module pinout.
26 April 2022
- 00:2600:26, 26 April 2022 diff hist +5 m PPU registers Improves mosaic size description.
- 00:1500:15, 26 April 2022 diff hist +22 m PPU registers Fixes mosaic size.
- 00:1200:12, 26 April 2022 diff hist −2 m PPU registers Minor fixes.
- 00:0300:03, 26 April 2022 diff hist +5,860 N PPU registers Starts the PPU registers page.
25 April 2022
- 05:2105:21, 25 April 2022 diff hist +18 m APU pinout Fixes Fievel Goes West title.
- 05:0505:05, 25 April 2022 diff hist +381 APU pinout Adds information about DSP input clock.
- 04:5104:51, 25 April 2022 diff hist +5,352 N Tricky-to-emulate games Adds Sour's tricky-to-emulate games findings.
- 02:0102:01, 25 April 2022 diff hist +7,794 N APU pinout Adds S-SMP and S-DSP pinouts.
- 01:5401:54, 25 April 2022 diff hist +383 CPU pinout Adds VPA, VDA, unknown clocks. Renames address and data pins to be more explicit.
- 01:1101:11, 25 April 2022 diff hist +138 Cartridge connector Renames CPU lines to be more explicit.
24 April 2022
- 23:5623:56, 24 April 2022 diff hist 0 PPU pinout Renames CPU lines to be more explicit.
- 04:5804:58, 24 April 2022 diff hist +269 PPU pinout Adds more test pin info and relevant reference.
- 01:2701:27, 24 April 2022 diff hist +192 PPU pinout Adds unknown direction to key.
- 00:5900:59, 24 April 2022 diff hist +105 PPU pinout Renames /TOUMEI to /TRANSPARENT and adds suspected behavior.
- 00:1900:19, 24 April 2022 diff hist +162 PPU pinout Adds a reference for digital video out.
- 00:0600:06, 24 April 2022 diff hist +5,213 PPU pinout Adds S-PPU2 pinout.
23 April 2022
- 23:3423:34, 23 April 2022 diff hist +16 PPU pinout Minor direction and naming changes.
- 21:4921:49, 23 April 2022 diff hist 0 m PPU pinout Copy/paste fix.
- 07:5307:53, 23 April 2022 diff hist +4,841 N PPU pinout Adds S-PPU1 pinout.
- 07:3007:30, 23 April 2022 diff hist −2 CPU pinout Changes /PAWR and /PARD to /PWR and /PRD.
- 07:2907:29, 23 April 2022 diff hist −6 Cartridge connector Changes /PAWR and /PARD to /PWR and /PRD.
- 04:3904:39, 23 April 2022 diff hist +21 Cartridge connector Adds pinout category to cartridge connector.
- 04:3904:39, 23 April 2022 diff hist 0 N Category:Pinouts Creates the Pinouts category. current
- 04:3804:38, 23 April 2022 diff hist +4,771 N CPU pinout Adds the CPU pinout.
- 00:2600:26, 23 April 2022 diff hist +306 Cartridge connector →Signal descriptions
- 00:1100:11, 23 April 2022 diff hist +2,117 N Cartridge connector Adds a cartridge connector pinout page.