Timing: Difference between revisions
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Rainwarrior (talk | contribs) (some basic timing information) |
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* 8-cycles for internal WRAM. | * 8-cycles for internal WRAM. | ||
* 6-cycles for most [[MMIO registers]]. | * 6-cycles for most [[MMIO registers]]. | ||
* 12-cycles for [[MMIO registers#JOYSER0]] | * 12-cycles for [[MMIO registers#JOYSER0|JOYSER0 and JOYSER1]]. | ||
* 6-cycles for "internal" cycles not accessing memory (e.g. 2nd cycle of NOP) | * 6-cycles for "internal" cycles not accessing memory (e.g. 2nd cycle of NOP) | ||
== References == | == References == | ||
<References/> | <References/> | ||
Revision as of 03:52, 26 May 2022
The SNES master clock:
- NTSC 21.447 MHz
- PAL 21.281 MHz
A 65816 CPU "cycle" can take 6, 8 or 12 master cycles on the SNES, depending on the memory region accessed, and the MEMSEL fast-ROM setting.
This gives some commonly quoted SNES CPU speeds, though none of them tell a complete story:
- 3.58 MHz fast-ROM (6-cycle)
- 2.68 MHz slow-ROM (8-cycle)
- 1.79 MHz other (12-cycle)
The speed of access depends on the memory region:[1]
- 6-cycles for fast-ROM access, enabled via MEMSEL and accessed at an address of $800000 of higher.
- 8-cycles for slow-ROM access.
- 8-cycles for internal WRAM.
- 6-cycles for most MMIO registers.
- 12-cycles for JOYSER0 and JOYSER1.
- 6-cycles for "internal" cycles not accessing memory (e.g. 2nd cycle of NOP)
