DMA registers: Revision history

25 February 2024

• curprev 20:2620:26, 25 February 2024‎ Tepples talk contribs‎ 13,536 bytes +234‎ →‎BBADn - B-bus address ($43n1 read/write) (n = 0..7): I forget: are we repeating errata in the register descriptions or not?

7 October 2022

• curprev 21:0421:04, 7 October 2022‎ Rainwarrior talk contribs‎ m 13,302 bytes +20‎ →‎See Also
• curprev 21:0321:03, 7 October 2022‎ Rainwarrior talk contribs‎ 13,282 bytes +35‎ link DMA examples

29 September 2022

• curprev 09:1109:11, 29 September 2022‎ Rainwarrior talk contribs‎ 13,247 bytes +560‎ →‎MDMAEN - Start DMA transfer ($420B write): noting post-conditions of DMA and how they might be efficiently chained

27 September 2022

• curprev 20:3120:31, 27 September 2022‎ Rainwarrior talk contribs‎ 12,687 bytes +151‎ →‎MDMAEN - Start DMA transfer ($420B write): odd timing note

20 August 2022

• curprev 08:4508:45, 20 August 2022‎ Rainwarrior talk contribs‎ 12,536 bytes +118‎ link SnesLab HDMA document

13 August 2022

• curprev 03:1603:16, 13 August 2022‎ Rainwarrior talk contribs‎ 12,418 bytes +332‎ →‎Line count, repeat mode byte: X-1 is confusing/wrong? It waits for exactly X scanlines. X=1 does not wait 0 scanlines. Adding a note below that might clarify?

5 June 2022

• curprev 08:3008:30, 5 June 2022‎ Rainwarrior talk contribs‎ 12,086 bytes +120‎ →‎Configuration registers (DMA): note that not all A bus addresses are valid

29 May 2022

• curprev 22:2822:28, 29 May 2022‎ Rainwarrior talk contribs‎ 11,966 bytes +49‎ →‎DMA channels: explain that they are shared
• curprev 22:2622:26, 29 May 2022‎ Rainwarrior talk contribs‎ 11,917 bytes +31‎ bolding DMA and HDMA, giving a definition for the H
• curprev 22:2322:23, 29 May 2022‎ Rainwarrior talk contribs‎ 11,886 bytes +50‎ link examples to they're easy to find
• curprev 22:2122:21, 29 May 2022‎ Rainwarrior talk contribs‎ 11,836 bytes +204‎ note the crash bug

25 May 2022

• curprev 08:1208:12, 25 May 2022‎ Fiskbit talk contribs‎ 11,632 bytes +106‎ Clarifies the DMA RAM copy limitation.
• curprev 07:2807:28, 25 May 2022‎ Fiskbit talk contribs‎ 11,526 bytes +125‎ Adds CPU and peripheral bus names to the intro. Elaborates a bit on what DMA is doing to explain why transfers must be cross-bus.
• curprev 06:0906:09, 25 May 2022‎ Fiskbit talk contribs‎ m 11,401 bytes +1‎ →‎NLTRn - HDMA Line-Counter ($43nA read/write) (n = 0..7): Adds missing n suffix to NLTR.
• curprev 06:0806:08, 25 May 2022‎ Fiskbit talk contribs‎ m 11,400 bytes 0‎ Fixes register name: NTRL -> NLTR.
• curprev 06:0706:07, 25 May 2022‎ Fiskbit talk contribs‎ 11,400 bytes +400‎ Adds power-on and reset info for each register.

24 May 2022

• curprev 20:2620:26, 24 May 2022‎ Rainwarrior talk contribs‎ 11,000 bytes +94‎ →‎BBADn - B-bus address ($43n1 read/write) (n = 0..7): describe potential B-bus targets
• curprev 20:2220:22, 24 May 2022‎ Rainwarrior talk contribs‎ 10,906 bytes +183‎ →‎DMAPn - DMA/HDMA parameters ($43n0 read/write) (n = 0..7): put "HDMA" in the bytes column, revise description of transfer pattern slightly, describe fixed increment fill technique
• curprev 19:2719:27, 24 May 2022‎ Rainwarrior talk contribs‎ 10,723 bytes −46‎ →‎DMAPn - DMA/HDMA parameters ($43n0 read/write) (n = 0..7): suggest droping the "xx", i find the visual noise difficult to parse
• curprev 19:2219:22, 24 May 2022‎ Rainwarrior talk contribs‎ 10,769 bytes +47‎ →‎A1TnL, A1TnH, A1Bn - HDMA Table Start Address ($43n2, $43n3, $43n4 read/write) (n = 0..7): "every frame" doesn't seem correct, rather it's just the start of an active HDMA?
• curprev 19:0719:07, 24 May 2022‎ Rainwarrior talk contribs‎ m 10,722 bytes −11‎ →‎DMAPn - DMA/HDMA parameters ($43n0 read/write) (n = 0..7): maybe I shouldn't say equivalent, parenthesize notes
• curprev 19:0419:04, 24 May 2022‎ Rainwarrior talk contribs‎ m 10,733 bytes +13‎ →‎DMAPn - DMA/HDMA parameters ($43n0 read/write) (n = 0..7): 5 is undocumented
• curprev 19:0419:04, 24 May 2022‎ Rainwarrior talk contribs‎ 10,720 bytes −14‎ →‎DMAPn - DMA/HDMA parameters ($43n0 read/write) (n = 0..7): pattern 7 seems to have an error, should be same as 3 according to fullsnes? (correct my error making 5 symmetrical, the length is important for HDMA)
• curprev 18:5318:53, 24 May 2022‎ Rainwarrior talk contribs‎ 10,734 bytes +14‎ →‎DMAPn - DMA/HDMA parameters ($43n0 read/write) (n = 0..7): pattern 5 is also an undocumented duplicate
• curprev 18:5018:50, 24 May 2022‎ Rainwarrior talk contribs‎ 10,720 bytes +42‎ →‎DMAPn - DMA/HDMA parameters ($43n0 read/write) (n = 0..7): mention 0-2 equivalence, 6-7 undocumented
• curprev 11:5911:59, 24 May 2022‎ Fiskbit talk contribs‎ m 10,678 bytes +11‎ Notes n range in table.
• curprev 05:2405:24, 24 May 2022‎ Rainwarrior talk contribs‎ 10,667 bytes +6‎ cleaning up some of my muddled descriptions
• curprev 05:1805:18, 24 May 2022‎ Rainwarrior talk contribs‎ 10,661 bytes +446‎ DASBn should be listed as an HDMA configuration register
• curprev 00:5600:56, 24 May 2022‎ Rainwarrior talk contribs‎ m 10,215 bytes +1‎ DASBn typo

23 May 2022

• curprev 23:5223:52, 23 May 2022‎ Rainwarrior talk contribs‎ m 10,214 bytes 0‎ DASBn is the preferred name?
• curprev 23:4823:48, 23 May 2022‎ Rainwarrior talk contribs‎ m 10,214 bytes 0‎ DASnB typo
• curprev 23:4723:47, 23 May 2022‎ Rainwarrior talk contribs‎ 10,214 bytes −21‎ consolidation and intra-page links to work better with the table access
• curprev 23:0823:08, 23 May 2022‎ Rainwarrior talk contribs‎ 10,235 bytes +310‎ separate entries for MDMAEN/HDMAEN
• curprev 22:5722:57, 23 May 2022‎ Rainwarrior talk contribs‎ 9,925 bytes +205‎ anchors for register definitions
• curprev 22:4022:40, 23 May 2022‎ Rainwarrior talk contribs‎ 9,720 bytes +397‎ adding register table stub

17 May 2022

• curprev 05:3205:32, 17 May 2022‎ Rainwarrior talk contribs‎ m 9,323 bytes +8‎ mvn/mvp links

16 May 2022

• curprev 19:3519:35, 16 May 2022‎ Fiskbit talk contribs‎ m 9,315 bytes +300‎ Uses fixed-width, non-wrapping text for target addresses.

13 May 2022

• curprev 17:2517:25, 13 May 2022‎ Fiskbit talk contribs‎ 9,015 bytes +209‎ Some clarity improvements. (Using n with a range instead of x for registers to make it clear there are 8 unique registers of each type, not 16 and not with any mirroring. Using x for readable unused bit and specifying it's unused, not open bus. Trying to make even more clear that the multi-address unused byte is just one byte at both addresses. Improving the pattern table.)

9 May 2022

• curprev 15:4915:49, 9 May 2022‎ NovaSquirrel talk contribs‎ 8,806 bytes +116‎ Add register names to some bit diagrams
• curprev 04:1804:18, 9 May 2022‎ NovaSquirrel talk contribs‎ 8,690 bytes +8,690‎ Created page with "The SNES's DMA (Direct Memory Access) unit allows a game to copy graphics, palettes, OAM and more at a much higher speed than the CPU can accomplish alone. This allows a game to make better use of the limited amount of time it has in vblank to change graphical memory. The SNES has two address buses - consisting of the A bus (which contains cartridge ROM, cartridge RAM, and the SNES's RAM) and the B bus (anything in the $2100-$21ff range, including PPU registers..."