User contributions for Fiskbit
From SNESdev Wiki
Jump to navigationJump to search
17 May 2024
- 23:1823:18, 17 May 2024 diff hist 0 m ROM header Fixes typo (compliment -> complement).
8 February 2024
- 22:1222:12, 8 February 2024 diff hist +2 m PPU registers →CGDATAREAD - CGRAM data read ($213B read twice): Formatting.
23 January 2024
- 06:3606:36, 23 January 2024 diff hist −1 m ROM header →Non Power-of-2 ROM Size: but -> so
- 06:3406:34, 23 January 2024 diff hist −8 ROM header →Checksum: Minor edits for flow. Removes 'to save size' (there are arguably multiple reasons why ROMs don't contain data duplicates).
- 05:0305:03, 23 January 2024 diff hist +160 m ROM header →Checksum: Mentions that for most non-power-of-2 ROMs, resizing is just duplicating the last third.
- 04:2504:25, 23 January 2024 diff hist +252 ROM header →Checksum: Fixes checksum to use bytes instead of words. Clarifies comment about adding a value and its complement. Rewords things to maybe be a bit clearer and not bury the lede. Minor formatting changes.
12 January 2024
- 10:4710:47, 12 January 2024 diff hist 0 m Controller connector Fixes JOY register typo. current
- 09:3909:39, 12 January 2024 diff hist +344 Controller connector Reformats the pinout to match our typical layout (names and directions in the diagram). De-densifies the information. Adds more detailed signal descriptions.
11 January 2024
- 21:0521:05, 11 January 2024 diff hist −16 Open bus 5A22 register reads are not visible externally. (e.g. SD2SNES requires code hooks to get joypad state.) current
- 16:1716:17, 11 January 2024 diff hist +1,863 Open bus Makes this page more accurate and detailed. Adds decay time reference.
10 January 2024
- 11:2711:27, 10 January 2024 diff hist +4 m PPU registers Explicitly notes that SLHV open bus is CPU open bus. Makes 'if' formatting on register access consistently use colon instead of comma.
19 October 2023
- 02:3902:39, 19 October 2023 diff hist +68 PPU pinout →Signal descriptions: EXTLATCH apparently connects to joypad 2 D1 on the Sharp SF-1 Super Famicom TV. Reported by l_oliveira.
23 August 2023
- 09:1509:15, 23 August 2023 diff hist +12 N MediaWiki:Mainpage Point to the new main page name. current
- 09:1409:14, 23 August 2023 diff hist +26 N Main Page Fiskbit moved page Main Page to SNESdev Wiki: Rename main page to match wiki name. current Tag: New redirect
- 09:1409:14, 23 August 2023 diff hist 0 m SNESdev Wiki Fiskbit moved page Main Page to SNESdev Wiki: Rename main page to match wiki name.
21 March 2023
- 10:0910:09, 21 March 2023 diff hist +18 m Reading and writing PPU memory Adds references category to separate out the references.
24 February 2023
- 16:3216:32, 24 February 2023 diff hist +287 N MediaWiki:Loginprompt Adds log-in prompt explaining how to register an account. current
3 June 2022
- 00:5800:58, 3 June 2022 diff hist 0 m CPU pinout Adds missing CPU prefix on A23. current
1 June 2022
- 04:1704:17, 1 June 2022 diff hist +599 Backgrounds Adds padding to priorities in BG mode table.
- 04:1304:13, 1 June 2022 diff hist +25 Sprites Notes which direction the priorities go in.
31 May 2022
- 11:5611:56, 31 May 2022 diff hist +9 m Errata More clarity on vblank NMI behavior.
- 11:5511:55, 31 May 2022 diff hist +249 Errata →Video: Further explains the behavior where enabling NMIs during vblank triggers an immediate NMI.
- 11:3211:32, 31 May 2022 diff hist +2 m Errata →References: Uses : to indent non-automated references to match automated ones.
30 May 2022
- 06:1106:11, 30 May 2022 diff hist 0 OAM layout Fixes sprite indices 0-15.
29 May 2022
- 00:3400:34, 29 May 2022 diff hist −3 MediaWiki:Sidebar Changes the SNES Discord link to make it more clear it's not run by NESdev staff. (Sidebar size limits prevent longer, more descriptive links here without ugly wrapping.) current
28 May 2022
- 08:2908:29, 28 May 2022 diff hist +2 m Mouse →References: Uses : to match indentation of automated references.
26 May 2022
- 07:4107:41, 26 May 2022 diff hist +856 WRAM pinout Names for connected signals, more signal descriptions, and corrections. current
- 04:4204:42, 26 May 2022 diff hist −2 m Tilemaps →Mode 7: Fix formatting.
- 04:3504:35, 26 May 2022 diff hist −2 m Tiles →8bpp Direct Color: Changes bit diagram so it doesn't suggest involvement of unrelated bits.
- 03:5203:52, 26 May 2022 diff hist +8 m Timing JOYSERn link formatting.
- 01:2701:27, 26 May 2022 diff hist +18 SNESdev Wiki →General: Adds CPU vectors link.
- 01:2401:24, 26 May 2022 diff hist +54 ROM header Adds interrupts back to the table as a single link to CPU vectors page.
- 01:2201:22, 26 May 2022 diff hist +16 CPU vectors Puts empty slots and ABORT into the tables.
- 01:0301:03, 26 May 2022 diff hist +26 ROM header Adds link to CPU vectors page.
- 01:0101:01, 26 May 2022 diff hist −722 ROM header Moves vectors to 'CPU vectors' page and adds $ prefix to addresses.
- 00:5600:56, 26 May 2022 diff hist +1,088 N CPU vectors Adds CPU vector page.
25 May 2022
- 23:3723:37, 25 May 2022 diff hist +72 Standard controller Notes the read behavior past first 16 reads.
- 23:3523:35, 25 May 2022 diff hist 0 m PPU registers →OAMADDL, OAMADDH - OAM word address ($2102, $2103 write): Fixes register address typo.
- 23:1623:16, 25 May 2022 diff hist −471 SNESdev Wiki Remove MediaWiki links that aren't relevant to standard contributors.
- 23:1423:14, 25 May 2022 diff hist +18 SNESdev Wiki →Pinouts: Adds WRAM pinout link.
- 23:1423:14, 25 May 2022 diff hist 0 m CPU pinout →Pinout: Minor formatting fix.
- 23:1323:13, 25 May 2022 diff hist 0 m PPU pinout →Pinout: Minor formatting fix.
- 23:1323:13, 25 May 2022 diff hist +2,454 N WRAM pinout Adds S-WRAM pinout.
- 09:3009:30, 25 May 2022 diff hist +466 MMIO registers →NMITIMEN - Interrupts and Joypad reading ($4200 write): Adds NMI details. Mentions the slight delay before auto-read starts. Improves auto-read description.
- 08:1208:12, 25 May 2022 diff hist +106 DMA registers Clarifies the DMA RAM copy limitation.
- 07:2807:28, 25 May 2022 diff hist +125 DMA registers Adds CPU and peripheral bus names to the intro. Elaborates a bit on what DMA is doing to explain why transfers must be cross-bus.
- 07:0607:06, 25 May 2022 diff hist −18 m Memory map Uses consistent, unambiguous units (KiB and MiB).
- 06:0906:09, 25 May 2022 diff hist +1 m DMA registers →NLTRn - HDMA Line-Counter ($43nA read/write) (n = 0..7): Adds missing n suffix to NLTR.
- 06:0806:08, 25 May 2022 diff hist 0 m MMIO register table/DMA Fixes register name: NTRL -> NLTR.
- 06:0806:08, 25 May 2022 diff hist 0 m DMA registers Fixes register name: NTRL -> NLTR.
