APU register table/SMP: Difference between revisions

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(Took the table from the S-SMP page, updated to match MMIO_register_table, added different register names and links)
 
(Update register bits (All TEST bits are used, DSPADDR bit 7 is used, TxOUT high-nibble is always 0))
Line 16: Line 16:
! Test
! Test
! $F0
! $F0
| style="text-align: right" | <tt style="white-space: nowrap">.I.E TRWH</tt>
| style="text-align: right" | <tt style="white-space: nowrap">IIEE TRWH</tt>
| W8
| W8
| Undocumented test register.
| Undocumented test register.
Line 30: Line 30:
! Register Address
! Register Address
! $F2
! $F2
| style="text-align: right" | <tt style="white-space: nowrap">.AAA AAAA</tt>
| style="text-align: right" | <tt style="white-space: nowrap">RAAA AAAA</tt>
| RW8
| RW8
| Selects a DSP register address.
| Selects a DSP register address.
Line 69: Line 69:
| Reads or writes data to [[MMIO registers#APUIO3|APUIO3]].
| Reads or writes data to [[MMIO registers#APUIO3|APUIO3]].
|-
|-
!
! ---
! ---
! $F8
! $F8
Line 76: Line 75:
| Unused (normal RAM).
| Unused (normal RAM).
|-
|-
!
! ---
! ---
! $F9
! $F9
Line 107: Line 105:
! Counter 0
! Counter 0
! $FD
! $FD
| style="text-align: right" | <tt style="white-space: nowrap">.... CCCC</tt>
| style="text-align: right" | <tt style="white-space: nowrap">0000 CCCC</tt>
| R8
| R8
| Timer 0 count-up.
| Timer 0 count-up.
Line 114: Line 112:
! Counter 1
! Counter 1
! $FE
! $FE
| style="text-align: right" | <tt style="white-space: nowrap">.... CCCC</tt>
| style="text-align: right" | <tt style="white-space: nowrap">0000 CCCC</tt>
| R8
| R8
| Timer 1 count-up.
| Timer 1 count-up.
Line 121: Line 119:
! Counter 2
! Counter 2
! $FF
! $FF
| style="text-align: right" | <tt style="white-space: nowrap">.... CCCC</tt>
| style="text-align: right" | <tt style="white-space: nowrap">0000 CCCC</tt>
| R8
| R8
| Timer 2 count-up.
| Timer 2 count-up.

Revision as of 10:03, 8 November 2024

See: APU register table

This table lists the 2 common names for the S-SMP registers.

Name Address Bits Type Notes
TEST Test $F0 IIEE TRWH W8 Undocumented test register.
CONTROL Control $F1 I.CC .210 W8 Enable IPL ROM (I), Clear data ports (C), timer enable (2,1,0).
DSPADDR Register Address $F2 RAAA AAAA RW8 Selects a DSP register address.
DSPDATA Register Data $F3 VVVV VVVV RW8 Reads or writes data to the selected DSP address.
CPUIO0 Port 0 $F4 VVVV VVVV RW8 Reads or writes data to APUIO0.
CPUIO1 Port 1 $F5 VVVV VVVV RW8 Reads or writes data to APUIO1.
CPUIO2 Port 2 $F6 VVVV VVVV RW8 Reads or writes data to APUIO2.
CPUIO3 Port 3 $F7 VVVV VVVV RW8 Reads or writes data to APUIO3.
--- $F8 .... .... RW8 Unused (normal RAM).
--- $F9 .... .... RW8 Unused (normal RAM).
T0TARGET Timer 0 $FA TTTT TTTT W8 8KHz timer 0 interval.
T1TARGET Timer 1 $FB TTTT TTTT W8 8KHz timer 1 interval.
T2TARGET Timer 2 $FC TTTT TTTT W8 64KHz timer 2 interval.
T0OUT Counter 0 $FD 0000 CCCC R8 Timer 0 count-up.
T1OUT Counter 1 $FE 0000 CCCC R8 Timer 1 count-up.
T2OUT Counter 2 $FF 0000 CCCC R8 Timer 2 count-up.