MMIO registers: Difference between revisions

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(Adds APU and S-WRAM registers.)
(Adds fastROM enable, power-on and reset values, and more APU register and math register details.)
Line 41: Line 41:
  |          11 = IRQ when V counter == VTIME and H counter == HTIME
  |          11 = IRQ when V counter == VTIME and H counter == HTIME
  +--------- Vblank NMI enable
  +--------- Vblank NMI enable
On power-on: NMITIMEN = $00
On reset:    NMITIMEN = $00


TODO: Details on the exact conditions for an NMI or IRQ.
* TODO: Details on the exact conditions for an NMI or IRQ.
 
* Auto-read runs at the beginning of vblank and is equivalent to writing 1 and then 0 to [[#JOYOUT|JOYOUT]] (to latch a standard controller) and then reading [[#JOYSER0|JOYSER0]] and [[#JOYSER1|JOYSER1]] 16 times each. The controllers are then left in this state so that additional reads can be done manually from JOYSER0 and JOYSER1 to get any additional data, though this is unnecessary for standard controllers. Auto-read takes approximately 3 scanlines, during which the JOYOUT, JOYSER0, and JOYSER1 registers should not be manually accessed. The resulting data can be read from the [[#JOY1|JOY1-4]] registers.
* Auto-read runs at the beginning of vblank and is equivalent to writing 1 and then 0 to [[#JOYOUT|JOYOUT]] (to latch a standard controller) and then reading [[#JOYSER0|JOYSER0]] and [[#JOYSER1|JOYSER1]] 16 times each. The controllers are then left in this state so that additional reads can be done manually from JOYSER0 and JOYSER1 to get any additional data, though this is unnecessary for standard controllers. Auto-read takes approximately 3 scanlines, during which the JOYOUT, JOYSER0, and JOYSER1 registers should not be manually accessed. The resulting data can be read from the [[#JOY1|JOY1-4]] registers.


Line 57: Line 59:
         |  |||| ||||
         |  |||| ||||
         +---++++-++++- H counter target for timer IRQ
         +---++++-++++- H counter target for timer IRQ
On power-on: HTIME = $1FF


Note that setting a value larger than the maximum H counter value of 339 will prevent the timer's H condition from being met.
Note that setting a value larger than the maximum H counter value of 339 will prevent the timer's H condition from being met.
Line 69: Line 73:
         |  |||| ||||
         |  |||| ||||
         +---++++-++++- V counter target for timer IRQ
         +---++++-++++- V counter target for timer IRQ
On power-on: VTIME = $1FF


Note that setting a value larger than the maximum V counter value will prevent the timer's V condition from being met. The maximum depends on the region (261 for NTSC, 311 for PAL) and interlacing (1 additional scanline every other frame).
Note that setting a value larger than the maximum V counter value will prevent the timer's V condition from being met. The maximum depends on the region (261 for NTSC, 311 for PAL) and interlacing (1 additional scanline every other frame).
Line 84: Line 90:
  +--------- Vblank flag
  +--------- Vblank flag
   
   
  On read: RDNMI D7 = 0
On power-on: RDNMI = RDNMI & $7F
On reset:    RDNMI = RDNMI & $7F
  On read:     RDNMI = RDNMI & $7F


The vblank flag is set at the start of vblank and cleared at the end of vblank or on read.
The vblank flag is set at the start of vblank and cleared at the end of vblank or on read.
Line 97: Line 105:
  +--------- Timer flag
  +--------- Timer flag
   
   
  On read: TIMEUP D7 = 0
On power-on: TIMEUP = TIMEUP & $7F
On reset:    TIMEUP = TIMEUP & $7F
  On read:     TIMEUP = TIMEUP & $7F


The timer flag is set when the timer condition specified in NMITIMEN becomes true and is cleared on read.
The timer flag is set when the timer condition specified in NMITIMEN becomes true and is cleared on read.
Line 128: Line 138:
  ++++-++++- Data from APU
  ++++-++++- Data from APU


When the SPC700 reads from $F4+n in its address space, it receives the last value written to APUIOn. When APUIOn is read, the value received is the last one written by the SPC700 to $F4+n.
When the SPC700 reads from $F4+n in its address space, it receives the last value written to APUIOn. When APUIOn is read, the value received is the last one written by the SPC700 to $F4+n. If APUIOn is read while its corresponding $F4+n register is being written, the value read will be the bitwise OR of the old and new values.
 
These registers are mirrored across $2140-217F.


==WRAM==
==WRAM==
Line 157: Line 169:


DMA from S-WRAM to these registers has no effect.
DMA from S-WRAM to these registers has no effect.
==ROM==
===MEMSEL - ROM access speed ($420D write)===
  7  bit  0
  ---- ----
  .... ...F
          |
          +- FastROM enable
On power-on: MEMSEL = $00
If enabled, ROM access to banks $80-FF takes only 6 system clock cycles instead of 8.


==Joypads==
==Joypads==
Line 209: Line 233:
  +--------- Joypad port 2 I/O, and
  +--------- Joypad port 2 I/O, and
             PPU /EXTLATCH light pen input
             PPU /EXTLATCH light pen input
On power-on: WRIO = $FF


{{Anchor|RDIO}}
{{Anchor|RDIO}}
Line 278: Line 304:
  |||| ||||
  |||| ||||
  ++++-++++- 8-bit multiplication factor (unsigned)
  ++++-++++- 8-bit multiplication factor (unsigned)
On power-on: WRMPYA = $FF


{{Anchor|WRMPYB}}
{{Anchor|WRMPYB}}
Line 288: Line 316:
   
   
  On write: Begins multiplication process
  On write: Begins multiplication process
The multiplication process takes up to 8 CPU cycles and the result is written to RDMPY as it goes. See 5A22 [[Multiplication]] for more information.


===Division===
===Division===
Line 300: Line 330:
  |||| ||||  |||| ||||
  |||| ||||  |||| ||||
  ++++-++++---++++-++++- 16-bit dividend (unsigned)
  ++++-++++---++++-++++- 16-bit dividend (unsigned)
On power-on: WRDIV = $FFFF


{{Anchor|WRDIVB}}
{{Anchor|WRDIVB}}
Line 310: Line 342:
   
   
  On write: Begins division process
  On write: Begins division process
The division process takes up to 16 CPU cycles and the result is written to RDDIV (quotient) and RDMPY (remainder) as it goes. Dividing by 0 results in a quotient of $FFFF and a remainder equal to the dividend (WRDIV).


===Result===
===Result===

Revision as of 13:46, 23 May 2022

TODO

  • $2100-213F PPU registers
  • $2140-2413 APUIO
  • $2180 WMDATA
  • $2181-2183 WMADD
  • $4016 Legacy Gamepad 1
  • $4017 Legacy Gamepad 2
  • $4200 NMITIMEN
  • $4201 WRIO
  • $4202-4203 WRMPY
  • $4204-4206 WRDIV
  • $4207-4208 HTIME
  • $4209-420A VTIME
  • $420B MDMAEN
  • $420C HDMAEN
  • $420D MEMSEL
  • $420E-420F ?
  • $4210 RDNMI
  • $4211 TIMEUP
  • $4212 HVBJOY
  • $4213 RDIO
  • $4214-4215 RDDIV
  • $4216-4217 RDMPY
  • $4218-421F STD CNTRL1-4
  • $4300-437F DMA registers

Interrupts

NMITIMEN - Interrupts and Joypad reading ($4200 write)

7  bit  0
---- ----
N.VH ...J
| ||    |
| ||    +- Joypad auto-read enable
| ++------ H/V timer IRQ:
|           00 = Disable timer
|           01 = IRQ when H counter == HTIME
|           10 = IRQ when V counter == VTIME and H counter == 0
|           11 = IRQ when V counter == VTIME and H counter == HTIME
+--------- Vblank NMI enable

On power-on: NMITIMEN = $00
On reset:    NMITIMEN = $00
  • TODO: Details on the exact conditions for an NMI or IRQ.
  • Auto-read runs at the beginning of vblank and is equivalent to writing 1 and then 0 to JOYOUT (to latch a standard controller) and then reading JOYSER0 and JOYSER1 16 times each. The controllers are then left in this state so that additional reads can be done manually from JOYSER0 and JOYSER1 to get any additional data, though this is unnecessary for standard controllers. Auto-read takes approximately 3 scanlines, during which the JOYOUT, JOYSER0, and JOYSER1 registers should not be manually accessed. The resulting data can be read from the JOY1-4 registers.

Screen timer values

HTIMEL, HTIMEH - H timer target ($4207, $4208 write)

  HTIMEH      HTIMEL
  $4208       $4207
7  bit  0   7  bit  0
---- ----   ---- ----
.... ...H   HHHH HHHH
        |   |||| ||||
        +---++++-++++- H counter target for timer IRQ

On power-on: HTIME = $1FF

Note that setting a value larger than the maximum H counter value of 339 will prevent the timer's H condition from being met.

VTIMEL, VTIMEH - V timer target ($4209, $420A write)

  VTIMEH      VTIMEL
  $420A       $4209
7  bit  0   7  bit  0
---- ----   ---- ----
.... ...V   VVVV VVVV
        |   |||| ||||
        +---++++-++++- V counter target for timer IRQ

On power-on: VTIME = $1FF

Note that setting a value larger than the maximum V counter value will prevent the timer's V condition from being met. The maximum depends on the region (261 for NTSC, 311 for PAL) and interlacing (1 additional scanline every other frame).

Status

RDNMI - Vblank flag and CPU version ($4210 read)

7  bit  0
---- ----
Nxxx VVVV
|||| ||||
|||| ++++- CPU version
|+++------ (Open bus)
+--------- Vblank flag

On power-on: RDNMI = RDNMI & $7F
On reset:    RDNMI = RDNMI & $7F
On read:     RDNMI = RDNMI & $7F

The vblank flag is set at the start of vblank and cleared at the end of vblank or on read.

TIMEUP - Timer flag ($4211 read)

7  bit  0
---- ----
Txxx xxxx
|||| ||||
|+++-++++- (Open bus)
+--------- Timer flag

On power-on: TIMEUP = TIMEUP & $7F
On reset:    TIMEUP = TIMEUP & $7F
On read:     TIMEUP = TIMEUP & $7F

The timer flag is set when the timer condition specified in NMITIMEN becomes true and is cleared on read.

HVBJOY - Screen and Joypad status ($4212 read)

7  bit  0
---- ----
VHxx xxxJ
|||| ||||
|||| |||+- Joypad auto-read in-progress flag
||++-+++-- (Open bus)
|+-------- Hblank flag
+--------- Vblank flag

APU

APUIOn - Data-to-APU register n ($214n write) (n = 0..3)

7  bit  0
---- ----
DDDD DDDD
|||| ||||
++++-++++- Data to APU

APUIOn - Data-from-APU register n ($214n read) (n = 0..3)

7  bit  0
---- ----
DDDD DDDD
|||| ||||
++++-++++- Data from APU

When the SPC700 reads from $F4+n in its address space, it receives the last value written to APUIOn. When APUIOn is read, the value received is the last one written by the SPC700 to $F4+n. If APUIOn is read while its corresponding $F4+n register is being written, the value read will be the bitwise OR of the old and new values.

These registers are mirrored across $2140-217F.

WRAM

WMDATA - S-WRAM data access ($2180 read/write)

7  bit  0
---- ----
DDDD DDDD
|||| ||||
++++-++++- S-WRAM data

On write: [WMADD] = value
          WMADD = WMADD + 1

This register's presence on the peripheral bus allows DMA between S-WRAM and another, different source. Because DMA simultaneously accesses the source and destination, S-WRAM cannot succesfully be both because it cannot simultaneously read from and write to itself. DMA from S-WRAM to this register has no effect, and DMA from this register to S-WRAM writes open bus. In both cases, the address is not incremented.

WMADDL, WMADDM, WMADDH - S-WRAM address ($2181, $2182, $2183 write)

  WMADDH      WMADDM      WMADDL
  $2183       $2182       $2181
7  bit  0   7  bit  0   7  bit  0
---- ----   ---- ----   ---- ----
.... ...H   MMMM MMMM   LLLL LLLL
        |   |||| ||||   |||| ||||
        +---++++-++++---++++-++++- S-WRAM address for WMDATA

DMA from S-WRAM to these registers has no effect.

ROM

MEMSEL - ROM access speed ($420D write)

 7  bit  0
 ---- ----
 .... ...F
         |
         +- FastROM enable

On power-on: MEMSEL = $00

If enabled, ROM access to banks $80-FF takes only 6 system clock cycles instead of 8.

Joypads

Joypad NES-style interface

JOYOUT - Joypad output ($4016 write)

7  bit  0
---- ----
.... .210
      |||
      ||+- OUT0
      ++-- OUT2-1 (not connected)

OUT0 is used by standard controllers to latch the current button state. OUT2-1 are not connected in standard consoles, but may be used in the Super Famicom Box hotel system.

JOYSER0 - Joypad serial data port 1 ($4016 read)

7  bit  0
---- ----
xxxx xxDD
|||| ||||
|||| ||++- Joypad port 1 data 2-1
++++-++--- (Open bus)

On read: Joypad port 1 is clocked (via joypad 1 /OE)

JOYSER1 - Joypad serial data port 2 ($4017 read)

7  bit  0
---- ----
xxx1 11DD
|||| ||||
|||| ||++- Joypad port 2 data 2-1
|||+-++--- Joypad 2 D4-2 (always 1)
+++------- (Open bus)

On read: Joypad port 2 is clocked (via joypad 2 /OE)

The CPU has 5 joypad 2 inputs. Joypad port 2's data 2 and 1 pins connect to D1-0, while D4-2 are tied to ground (and thus read as 1).

Joypad I/O interface

WRIO - Write I/O ($4201 write)

7  bit  0
---- ----
21DD DDDD
|||| ||||
||++-++++- CPU I/O D5-0 (not connected)
|+-------- Joypad port 1 I/O
+--------- Joypad port 2 I/O, and
           PPU /EXTLATCH light pen input

On power-on: WRIO = $FF

RDIO - Read I/O ($4213 read)

7  bit  0
---- ----
21DD DDDD
|||| ||||
||++-++++- CPU I/O D5-0 (not connected)
|+-------- Joypad port 1 I/O
+--------- Joypad port 2 I/O

The I/O pins allow bidirectional communication between the CPU and joypads on a single wire per bit. Either side is able to set the bits to 0, so to read the value being sent by the other side, the reader must set its own corresponding bits to 1 before reading.

The not-connected D5-0 bits can be used as general-purpose storage on standard consoles, but are used in the Super Famicom Box hotel system to communicate with its HD64180 CPU.

Joypad port 2's I/O bit is also connected to the PPU's /EXTLATCH input, allowing the PPU's H and V counters to be latched when this bit is set to 0 by the CPU or joypad. This is intended to support a light pen or gun device. This should normally be set to 1 by the CPU to allow the counters to be latched. (See PPU registers)

Auto-read results

JOY1L, JOY1H - Joypad port 1 data 1 ($4218, $4219 read)

  JOY1H       JOY1L
  $4219       $4218
7  bit  0   7  bit  0
---- ----   ---- ----
DDDD DDDD   DDDD DDDD
|||| ||||   |||| ||||
++++-++++---++++-++++- Joypad port 1 data 1 (first read on left to last read on right)

JOY2L, JOY2H - Joypad port 2 data 1 ($421A, $421B read)

  JOY2H       JOY2L
  $421B       $421A
7  bit  0   7  bit  0
---- ----   ---- ----
DDDD DDDD   DDDD DDDD
|||| ||||   |||| ||||
++++-++++---++++-++++- Joypad port 2 data 1 (first read on left to last read on right)

JOY3L, JOY3H - Joypad port 1 data 2 ($421C, $421D read)

  JOY3H       JOY3L
  $421D       $421C
7  bit  0   7  bit  0
---- ----   ---- ----
DDDD DDDD   DDDD DDDD
|||| ||||   |||| ||||
++++-++++---++++-++++- Joypad port 1 data 2 (first read on left to last read on right)

JOY4L, JOY4H - Joypad port 2 data 2 ($421E, $421F read)

  JOY4H       JOY4L
  $421F       $421E
7  bit  0   7  bit  0
---- ----   ---- ----
DDDD DDDD   DDDD DDDD
|||| ||||   |||| ||||
++++-++++---++++-++++- Joypad port 2 data 2 (first read on left to last read on right)

Math

Multiplication

WRMPYA - Multiplication factor A ($4202 write)

7  bit  0
---- ----
DDDD DDDD
|||| ||||
++++-++++- 8-bit multiplication factor (unsigned)

On power-on: WRMPYA = $FF

WRMPYB - Multiplication factor B ($4203 write)

7  bit  0
---- ----
DDDD DDDD
|||| ||||
++++-++++- 8-bit multiplication factor (unsigned)

On write: Begins multiplication process

The multiplication process takes up to 8 CPU cycles and the result is written to RDMPY as it goes. See 5A22 Multiplication for more information.

Division

WRDIVL, WRDIVH - Dividend ($4204, $4205 write)

  WRDIVH      WRDIVL
  $4205       $4204
7  bit  0   7  bit  0
---- ----   ---- ----
HHHH HHHH   LLLL LLLL
|||| ||||   |||| ||||
++++-++++---++++-++++- 16-bit dividend (unsigned)

On power-on: WRDIV = $FFFF

WRDIVB - Divisor ($4206 write)

7  bit  0
---- ----
DDDD DDDD
|||| ||||
++++-++++- 8-bit divisor (unsigned)

On write: Begins division process

The division process takes up to 16 CPU cycles and the result is written to RDDIV (quotient) and RDMPY (remainder) as it goes. Dividing by 0 results in a quotient of $FFFF and a remainder equal to the dividend (WRDIV).

Result

RDDIVL, RDDIVH - Quotient ($4214, $4215 read)

  RDDIVH      RDDIVL
  $4215       $4214
7  bit  0   7  bit  0
---- ----   ---- ----
HHHH HHHH   LLLL LLLL
|||| ||||   |||| ||||
++++-++++---++++-++++- 16-bit quotient (unsigned)

RDMPYL, RDMPYH - Product or Remainder ($4216, $4217 read)

  RDMPYH      RDMPYL
  $4217       $4216
7  bit  0   7  bit  0
---- ----   ---- ----
HHHH HHHH   LLLL LLLL
|||| ||||   |||| ||||
++++-++++---++++-++++- 16-bit product (unsigned), or
                       16-bit remainder (unsigned)
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