S-SMP

The SPC700 is the CPU portion of the S-SMP processor used to run the sound and music of the SNES. It is an 8-bit CPU with capabilities similar to the 6502.

Memory Layout

TODO

Registers

TODO

DSP Registers

A DSP register can be selected with $F2, after which it can be read or written via $FE. Often it is useful to load the register address into A, and the value to send in Y, so that MOV $F2, AY can be used to do both in one 16-bit instruction.

Voices

There are 8 voices, numbered 0 to 7. Each voice X has 10 registers in the range $X0-$X9.

Name	Address	Bits	Notes
VOL (L)	$X0	SVVV VVVV	Left channel volume, signed.
VOL (R)	$X1	SVVV VVVV	Right channel volume, signed.
P (L)	$X2	LLLL LLLL	Low 8 bits of sample pitch.
P (H)	$X3	xxHH HHHH	High 6 bits of sample pitch.
SCRN	$X4	SSSS SSSS	Selects a sample source entry from the directory (see DIR below).
ADSR (1)	$X5	EDDD AAAA	ADRS enable (E), decay rate (D), attack rate (A).
ADSR (2)	$X6	LLLR RRRR	Sustain level (L), sustain rate (R).
GAIN	$X7	0VVV VVVV 1MMV VVVV	Mode (M), value (V).
ENVX	$X8	0VVV VVVV	Reads current 7-bit value of ADSR/GAIN envelope.
OUTX	$X9	SVVV VVVV	Reads signed 8-bit value of current sample wave multiplied by ENVX, before applying VOL.

SCRN

This points to an entry in the sample source directory (DIR). Changing this will not immediately change the voice's sample without a key on (KON), but if a looping sample is playing it can be used to change the loop point without a key on.

ADSR

This controls an Attack-Decay-Sustain-Release envelope that automatically adjusts the sample's envelope volume (ENVX) over time.

• E: 1 to enable ADSR envelope, otherwise uses GAIN directly.
• A: Attack speed. $F for instant.
• D: Decay speed, time to decay from full volume to the sustain level after the initial attack.
• L: Sustain level.
• R: Sustain release, speed of decay to 0 after note off.

GAIN

This register has 5 modes:

• 0VVV VVVV sets ENVX directly.
• 110V VVVV Linear slide up to 100% volume with rate V.
• 111V VVVV Bent-line (fast to 75%, then slower to 100%) slide up with rate V.
• 100V VVVV Linear slide down to 0% volume with rate V.
• 101V VVVV Exponential slide down to 0% volume with rate V.

Global

Other DSP registers apply globally, rather than to a specific voice.

Name	Address	Bits	Notes
MVOL (L)	$0C	SVVV VVVV	Left channel main volume, signed.
MVOL (R)	$1C	SVVV VVVV	Right channel main volume, signed.
EVOL (L)	$2C	SVVV VVVV	Left channel echo volume, signed.
EVOL (R)	$3C	SVVV VVVV	Right channel main volume, signed.
KON	$4C	7654 3210	Key on. Writing this with any bit set will start a new note for the corresponding voice.
KOF	$5C	7654 3210	Key off. Writing this with any bit set will put the corresponding voice into its release state.
FLG	$6C	RMEN NNNN	Flags: soft reset (R), mute all (M), echo disable (E), noise frequency (N).
ENDX	$7C	7654 3210	Read for end of sample flag for each channel.
EFB	$0D	SVVV VVVV	Echo feedback, signed.
-	$1D	---- ----	Unused.
PMON	$2D	7654 321-	Enables pitch modulation for each channel, controlled by OUTX of the next lower channel.
NON	$3D	7654 3210	For each channel, replaces the sample waveform with the noise generator output.
EON	$4D	7654 3210	For each channel, sends to the echo unit.
DIR	$5D	DDDD DDDD	Pointer to the sample source directory page at $DD00.
ESA	$6D	EEEE EEEE	Pointer to the start of the echo memory region at $EE00.
EDL	$7D	---- DDDD	Echo delay time (D).
C0	$0F	SVVV VVVV	Echo filter coefficient.
C1	$1F	SVVV VVVV	Echo filter coefficient.
C2	$2F	SVVV VVVV	Echo filter coefficient.
C3	$3F	SVVV VVVV	Echo filter coefficient.
C4	$4F	SVVV VVVV	Echo filter coefficient.
C5	$5F	SVVV VVVV	Echo filter coefficient.
C6	$6F	SVVV VVVV	Echo filter coefficient.
C7	$7F	SVVV VVVV	Echo filter coefficient.

KON

This immediately starts the sample from its beginning, as designated by SCRN. If ADSR is enabled, its envelope will also start from the beginning.

FLG

• R: soft reset prevents KON and mutes all voices.
• M: mutes all voices.
• E: set to 1 to disable echo, if 0 the echo unit will actively overwrite memory in the echo region (ESA). Do not write 0 to this bit unless ESA/EDL have been prepared.
• N: sets the noise generator frequency.

ENDX

Each bit will read as set once a voice has finished playing a BRR sample block with the Source End flag set. Writing any value to this register will reset all the bits to 0, otherwise they remain set until the voice receives a new note on (KON).

Instruction Set

Official instruction names and syntax for SPC-700 instruction were provided by Sony. However, because of its architectural similarity to 6502, some prefer to rename and remap them using a 6502 style syntax. Both are provided here.

SPC-700 Instruction Set

Instruction	6502-Style	Opcode	Bytes	Cycles	Flags	Notes
TODO

IPL Boot ROM

TODO

BRR Samples

TODO (See Links section below.)

See Also

• Booting the SPC700 - Guide for setting up the SPC program after reset.
• Tools - Lists tools for building SPC700 code.
• APU pinout - Chip pinouts.

Links

• SPC 700 Documentation - Article by Gau.
• SPC700 Reference - Superfamicom.org wiki article.
• Bit Rate Reduction - Superfamicom.org wiki article, documents BRR sample format.
• SNES APU DSP BRR Samples - Fullsnes documentation of BRR sample format.