APU register table/SMP: Difference between revisions
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(Update register bits (All TEST bits are used, DSPADDR bit 7 is used, TxOUT high-nibble is always 0)) |
(Fix misaligned $F8 and $F9 registers) |
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| Reads or writes data to [[MMIO registers#APUIO3|APUIO3]]. | | Reads or writes data to [[MMIO registers#APUIO3|APUIO3]]. | ||
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! --- | ! --- | ||
! $F8 | ! $F8 | ||
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| Unused (normal RAM). | | Unused (normal RAM). | ||
|- | |- | ||
! | |||
! --- | ! --- | ||
! $F9 | ! $F9 | ||
Revision as of 10:10, 8 November 2024
See: APU register table
This table lists the 2 common names for the S-SMP registers.
| Name | Address | Bits | Type | Notes | |
|---|---|---|---|---|---|
| TEST | Test | $F0 | IIEE TRWH | W8 | Undocumented test register. |
| CONTROL | Control | $F1 | I.CC .210 | W8 | Enable IPL ROM (I), Clear data ports (C), timer enable (2,1,0). |
| DSPADDR | Register Address | $F2 | RAAA AAAA | RW8 | Selects a DSP register address. |
| DSPDATA | Register Data | $F3 | VVVV VVVV | RW8 | Reads or writes data to the selected DSP address. |
| CPUIO0 | Port 0 | $F4 | VVVV VVVV | RW8 | Reads or writes data to APUIO0. |
| CPUIO1 | Port 1 | $F5 | VVVV VVVV | RW8 | Reads or writes data to APUIO1. |
| CPUIO2 | Port 2 | $F6 | VVVV VVVV | RW8 | Reads or writes data to APUIO2. |
| CPUIO3 | Port 3 | $F7 | VVVV VVVV | RW8 | Reads or writes data to APUIO3. |
| --- | $F8 | .... .... | RW8 | Unused (normal RAM). | |
| --- | $F9 | .... .... | RW8 | Unused (normal RAM). | |
| T0TARGET | Timer 0 | $FA | TTTT TTTT | W8 | 8KHz timer 0 interval. |
| T1TARGET | Timer 1 | $FB | TTTT TTTT | W8 | 8KHz timer 1 interval. |
| T2TARGET | Timer 2 | $FC | TTTT TTTT | W8 | 64KHz timer 2 interval. |
| T0OUT | Counter 0 | $FD | 0000 CCCC | R8 | Timer 0 count-up. |
| T1OUT | Counter 1 | $FE | 0000 CCCC | R8 | Timer 1 count-up. |
| T2OUT | Counter 2 | $FF | 0000 CCCC | R8 | Timer 2 count-up. |
