Cartridge connector: Difference between revisions
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(Adds pinout category to cartridge connector.) |
(Changes /PAWR and /PARD to /PWR and /PRD.) |
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| Line 8: | Line 8: | ||
EXPAND <> |02 33| -> REFRESH | EXPAND <> |02 33| -> REFRESH | ||
PA6 <- |03 34| -> PA7 | PA6 <- |03 34| -> PA7 | ||
/ | /PRD <- |04 35| -> /PWR | ||
GND -- |05 36| -- GND | GND -- |05 36| -- GND | ||
| Line 43: | Line 43: | ||
* '''EXPAND''': Connects to expansion port pin 24 and is pulled high. | * '''EXPAND''': Connects to expansion port pin 24 and is pulled high. | ||
* '''SYSTEM CLK''': 21.47727 MHz system clock. | * '''SYSTEM CLK''': 21.47727 MHz system clock. | ||
* '''PHI2''': This is the CPU clock output. When this signal is high, this means only that the CPU bus address is in a stable state. For both reads and writes, data is only guaranteed or required to be valid at the falling edge of this signal. /RD, /WR, / | * '''PHI2''': This is the CPU clock output. When this signal is high, this means only that the CPU bus address is in a stable state. For both reads and writes, data is only guaranteed or required to be valid at the falling edge of this signal. /RD, /WR, /PRD, and /PWR are normally used instead of this. | ||
* '''A23..0, /RD, /RW''': The CPU address bus, also known as the '''A bus'''. | * '''A23..0, /RD, /RW''': The CPU address bus, also known as the '''A bus'''. | ||
* '''A23..16''': Also known as bank address or '''BA7..0'''. | * '''A23..16''': Also known as bank address or '''BA7..0'''. | ||
* '''/ROMSEL''': Asserted when accessing ROM ($00-3F,80-BF:8000-FFFF, $40-7D,C0-FF:0000-FFFF). Also known as '''/CART'''. | * '''/ROMSEL''': Asserted when accessing ROM ($00-3F,80-BF:8000-FFFF, $40-7D,C0-FF:0000-FFFF). Also known as '''/CART'''. | ||
* '''/WRAMSEL''': Asserted when accessing work RAM ($00-3F,80-BF:0000-1FFF, $7E-7F:0000-FFFF). | * '''/WRAMSEL''': Asserted when accessing work RAM ($00-3F,80-BF:0000-1FFF, $7E-7F:0000-FFFF). | ||
* '''PA7..0, / | * '''PA7..0, /PRD, /PWR''': The peripheral address bus, also known as the '''B bus'''. | ||
* '''D7..0''': Data lines, shared between the CPU and peripheral buses. | * '''D7..0''': Data lines, shared between the CPU and peripheral buses. | ||
* '''CIC CLK''': Either 4 MHz or 3.072 MHz, depending on the console. | * '''CIC CLK''': Either 4 MHz or 3.072 MHz, depending on the console. | ||
Revision as of 07:29, 23 April 2022
Pinout
This diagram represents a top-down view looking directly into the connector. Pins 01-31 are the bottom side of the connector and label side of the cartridge.
SNES | Cart | SNES
(front) ------- (back)
SYSTEM CLK <- |01 32| -> /WRAMSEL
EXPAND <> |02 33| -> REFRESH
PA6 <- |03 34| -> PA7
/PRD <- |04 35| -> /PWR
GND -- |05 36| -- GND
A11 <- |06 37| -> A12
A10 <- |07 38| -> A13
A9 <- |08 39| -> A14
A8 <- |09 40| -> A15
A7 <- |10 41| -> A16
A6 <- |11 42| -> A17
A5 <- |12 43| -> A18
A4 <- |13 44| -> A19
A3 <- |14 45| -> A20
A2 <- |15 46| -> A21
A1 <- |16 47| -> A22
A0 <- |17 48| -> A23
/IRQ -> |18 49| -> /ROMSEL
D0 <> |19 50| <> D4
D1 <> |20 51| <> D5
D2 <> |21 52| <> D6
D3 <> |22 53| <> D7
/RD <- |23 54| -> /WR
CIC data 1 <> |24 55| <> CIC data 2
key CIC reset <- |25 56| <- CIC CLK
/reset <> |26 57| -> PHI2
+5V -- |27 58| -- +5V
PA0 <- |28 59| -> PA1
PA2 <- |29 60| -> PA3
PA4 <- |30 61| -> PA5
left audio in -> |31 62| <- right audio in
-------
Signal descriptions
- EXPAND: Connects to expansion port pin 24 and is pulled high.
- SYSTEM CLK: 21.47727 MHz system clock.
- PHI2: This is the CPU clock output. When this signal is high, this means only that the CPU bus address is in a stable state. For both reads and writes, data is only guaranteed or required to be valid at the falling edge of this signal. /RD, /WR, /PRD, and /PWR are normally used instead of this.
- A23..0, /RD, /RW: The CPU address bus, also known as the A bus.
- A23..16: Also known as bank address or BA7..0.
- /ROMSEL: Asserted when accessing ROM ($00-3F,80-BF:8000-FFFF, $40-7D,C0-FF:0000-FFFF). Also known as /CART.
- /WRAMSEL: Asserted when accessing work RAM ($00-3F,80-BF:0000-1FFF, $7E-7F:0000-FFFF).
- PA7..0, /PRD, /PWR: The peripheral address bus, also known as the B bus.
- D7..0: Data lines, shared between the CPU and peripheral buses.
- CIC CLK: Either 4 MHz or 3.072 MHz, depending on the console.
