Timing

Timing of the SNES hardware.

Master Clock

The SNES master clock:

• NTSC 21.447 MHz
• PAL 21.281 MHz

CPU

A 65816 CPU "cycle" can take 6, 8 or 12 master cycles on the SNES, depending on the memory region accessed, and the MEMSEL fast-ROM setting.

This gives some commonly quoted SNES CPU speeds, though none of them tell a complete story:

• 3.58 MHz fast-ROM (6-cycle)
• 2.68 MHz slow-ROM (8-cycle)
• 1.79 MHz other (12-cycle)

The speed of access depends on the memory region:

• 6-cycles for fast-ROM access, enabled via MEMSEL and accessed at an address of $800000 of higher.
• 8-cycles for slow-ROM access.
• 8-cycles for internal S-WRAM.
• 6-cycles for most MMIO registers.
• 12-cycles for JOYSER0 and JOYSER1.
• 6-cycles for "internal" cycles not accessing memory (e.g. 2nd cycle of NOP)

Video

Scanline

• 1364 master cycles = 341 dot cycles.
• The CPU pauses for 40 master cycles in the middle of each scanline for DRAM refresh, leaving 1324 active cycles per line.
• The left edge of the picture begins at cycle 88 of the line and continues until 1112.
• Scanline 0 is the end of vblank and beginning of rendering. It is hidden, and displays as a blank line.
• Scanlines 1-224 or 239 will normally render the visible image, unless force blanking is applied.
• Scanline 261 or 311 is the last line of vertical blank (NTSC or PAL), after which the next frame begins rendering.
• With interlacing on, 1 extra scanline will appear with each even frame, and one scanline outside the visible picture will be slightly shortened or lengthened for color synchronization.

Short and Long Scanlinces

• TODO

Vertical Blank

• Begins on vertical line V=225 or V=240 based on (SETINI overscan setting).
• Ends after vertical line V=261 (NTSC) or V=311 (PAL). The next line is V=0.
• This allows 37 (NTSC) or 87 (PAL) lines of vertical blank normally, or 22 (NTSC) / 72 (PAL) with overscan.
• With 1324 master cycles per line available, and DMA taking 8 cycles per byte, this gives an upper bound on DMA bandwidth per blank without forced blanking:

Region	Overscan	VBlank Lines	VBlank Cycles	DMA Bandwidth
NTSC	224	37	48,988	5.9 kb
NTSC	239	22	29,128	3.5 kb
PAL	224	87	115,188	14.0 kb
PAL	239	72	95,328	11.6 kb

Frame

The total cycles per frame is dependent on many factors:

• Some scanlines are slightly short or long.
• interlacing adds an extra scanline on even frames.
• DRAM refresh uses 40 cycles in the middle of each line.
• HDMA uses varying amounts of cycles just past the active part of each line.

Approximating a total, ignoring the factors above and assuming a constant number of cycles per scanline:

Region	Scanlines	Master Cycles	Available Cycles
NTSC	262	357,368	346,888
PAL	312	425,568	413,088

Tools

• SnesInstructionCycleTool - calculates CPU cycles and master clock cycles under different conditions