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Timing of the SNES hardware.

Master Clock

The SNES master clock:

  • NTSC 21.447 MHz
  • PAL 21.281 MHz


A 65816 CPU "cycle" can take 6, 8 or 12 master cycles on the SNES, depending on the memory region accessed, and the MEMSEL fast-ROM setting.

This gives some commonly quoted SNES CPU speeds, though none of them tell a complete story:

  • 3.58 MHz fast-ROM (6-cycle)
  • 2.68 MHz slow-ROM (8-cycle)
  • 1.79 MHz other (12-cycle)

The speed of access depends on the memory region:[1]

  • 6-cycles for fast-ROM access, enabled via MEMSEL and accessed at an address of $800000 of higher.
  • 8-cycles for slow-ROM access.
  • 8-cycles for internal S-WRAM.
  • 6-cycles for most MMIO registers.
  • 12-cycles for JOYSER0 and JOYSER1.
  • 6-cycles for "internal" cycles not accessing memory (e.g. 2nd cycle of NOP)



  • 1364 master cycles = 341 dot cycles

The CPU pauses for 40 master cycles in the middle of each scanline.


  • Cycles per frame
  • Scanlines per frame
  • Lines/cycles per vblank
  • Vblank DMA budgets


  1. Fullsnes: CPU Clock Cycles