Timing of the SNES hardware.
The SNES master clock:
- NTSC 21.447 MHz
- PAL 21.281 MHz
A 65816 CPU "cycle" can take 6, 8 or 12 master clocks on the SNES, depending on the memory region accessed, and the MEMSEL fast-ROM setting.
This gives some commonly quoted SNES CPU speeds, though none of them tell a complete story:
- 3.58 MHz fast-ROM (6-clocks per cycle)
- 2.68 MHz slow-ROM (8-clocks per cycle)
- 1.79 MHz other (12-clocks per cycle)
The speed of access depends on the memory region:
- 6-clocks for fast-ROM access, enabled via MEMSEL and accessed at an address of $800000 of higher.
- 8-clocks for slow-ROM access.
- 8-clocks for internal S-WRAM.
- 6-clocks for most MMIO registers.
- 12-clocks for JOYSER0 and JOYSER1.
- 6-clocks for "internal" cycles not accessing memory (e.g. 2nd cycle of NOP)
- 1364 master clocks = 341 dot cycles.
- The CPU pauses for 40 master clocks in the middle of each scanline for DRAM refresh, leaving 1324 active clocks per line.
- The left edge of the picture begins at clock 88 of the line and continues until 1112.
- Scanline 0 is the end of vblank and beginning of rendering. It is hidden, and displays as a blank line.
- Scanlines 1-224 or 239 will normally render the visible image, unless force blanking is applied.
- Scanline 261 or 311 is the last line of vertical blank (NTSC or PAL), after which the next frame begins rendering.
- With interlacing on, 1 extra scanline will appear with each even frame, and one scanline outside the visible picture will be slightly shortened or lengthened for color synchronization.
Short and Long Scanlines
Scanlines are normally 1364 master clocks, but there are two special cases:
- Short scanline: NTSC with interlace off, field=1, V=240.
- Long scanline: PAL with interlace on, field=1, V=311.
This means every odd frame may have one adjusted scanline, depending on the interlacing setting and region. It affects the same line regardless of the overscan setting.
These adjusted scanlines are always during vertical blank, so they do not affect the visible picture directly, but they are necessary to maintain synchronization with the colour signal.
- Normal: 1364 clocks, 340 dots. 336 dots of 4-clocks, 4 dots of 5-clocks.
- Long: 1368 clocks, 341 dots. 337 dots of 4-clocks, 4 dots of 5-clocks.
- Short: 1360 clocks, 340 dots. 340 dots of 4-clocks.
- Begins on vertical line V=225 or V=240 based on (SETINI overscan setting).
- Ends after vertical line V=261 (NTSC) or V=311 (PAL). The next line is V=0.
- This allows 37 (NTSC) or 87 (PAL) lines of vertical blank normally, or 22 (NTSC) / 72 (PAL) with overscan.
- With 1324 master clocks per line available, and DMA taking 8 clocks per byte, this gives an upper bound on DMA bandwidth per blank without forced blanking:
|Region||Overscan||VBlank Lines||VBlank Clocks||DMA Bandwidth|
The total clocks per frame is dependent on many factors:
- Some scanlines are slightly short or long.
- Interlacing adds an extra scanline on even frames.
- DRAM refresh uses 40 clocks in the middle of each line.
- HDMA uses varying amounts of clocks just past the active part of each line.
Approximating a total, ignoring the factors above and assuming a constant number of clocks per scanline:
|Region||Scanlines||Master Clocks||Available Clocks|
- SnesInstructionCycleTool - calculates CPU cycles and master clock cycles under different conditions
- Fullsnes: CPU Clock Cycles