User contributions for Fiskbit

22 May 2022

• 19:3319:33, 22 May 2022 diff hist +106‎ MMIO registers ‎ Auto-read description improvement.
• 19:2619:26, 22 May 2022 diff hist +53‎ MMIO registers ‎ Clarity improvements.
• 18:2318:23, 22 May 2022 diff hist +314‎ MMIO registers ‎ More precision regarding joypad bits.
• 17:3917:39, 22 May 2022 diff hist +3,695‎ MMIO registers ‎ Adds joypad registers.
• 16:2916:29, 22 May 2022 diff hist +86‎ m MMIO registers ‎ 16-bit register formatting.
• 16:1316:13, 22 May 2022 diff hist 0‎ m MMIO registers ‎ Formatting improvements.
• 16:1116:11, 22 May 2022 diff hist +2,197‎ MMIO registers ‎ Adds interrupt-related CPU registers.

19 May 2022

• 18:2318:23, 19 May 2022 diff hist −13‎ m PPU pinout ‎ Removes duplicate section header.

16 May 2022

• 20:2020:20, 16 May 2022 diff hist +71‎ m PPU registers ‎ Expands gaps between bytes in register definitions to 3 characters (enough to support 2-digit bit names on both sides).
• 19:3519:35, 16 May 2022 diff hist +300‎ m DMA registers ‎ Uses fixed-width, non-wrapping text for target addresses.
• 18:0218:02, 16 May 2022 diff hist 0‎ m PPU registers ‎ Corrects TS register address.
• 17:5517:55, 16 May 2022 diff hist +23‎ PPU registers ‎ Changes register summary type field to be more mobile-friendly. Adds types for each definition of a register (to more clearly distinguish W8 from W16).
• 16:4716:47, 16 May 2022 diff hist +584‎ PPU registers ‎ Changes register summary table formatting to match those on the NESdev wiki. Prevents wrapping between nybbles of individual bytes. Adds bit letters after each named item. Breaks out BG1 and M7 scroll register bit definitions because they're separate registers at the same address.
• 05:2005:20, 16 May 2022 diff hist −20‎ m Offset-per-tile ‎ Minor clarity improvements (hopefully).
• 04:4504:45, 16 May 2022 diff hist +24‎ m Offset-per-tile ‎ Minor formatting changes.

13 May 2022

• 17:2517:25, 13 May 2022 diff hist +209‎ DMA registers ‎ Some clarity improvements. (Using n with a range instead of x for registers to make it clear there are 8 unique registers of each type, not 16 and not with any mirroring. Using x for readable unused bit and specifying it's unused, not open bus. Trying to make even more clear that the multi-address unused byte is just one byte at both addresses. Improving the pattern table.)
• 16:5716:57, 13 May 2022 diff hist −123‎ PPU registers ‎ Merges low and high byte registers into combined definitions. Fixes on-write description for VMDATAxREAD

9 May 2022

• 04:4704:47, 9 May 2022 diff hist +78‎ PPU registers ‎ Explicitly notes which registers require 2 accesses.

8 May 2022

• 09:5809:58, 8 May 2022 diff hist +47‎ PPU registers ‎ Some minor formatting changes and consistent, unambiguous units. Formatting is in flux at these early stages and I'd love feedback, particularly as we add more content and see what does or doesn't work well. (Also, thank you so much for contributing! I actually found this to be one of the more-confusing registers while building this page.)

6 May 2022

• 15:4715:47, 6 May 2022 diff hist +1,753‎ PPU registers ‎ Adds OAM registers.
• 07:1407:14, 6 May 2022 diff hist +239‎ N MediaWiki:Sidebar ‎ Updates the sidebar.
• 05:4605:46, 6 May 2022 diff hist +19‎ PPU registers ‎ Another attempt at clearly explaining mode 7 tilemap boundary behavior.
• 05:2405:24, 6 May 2022 diff hist 0‎ m PPU registers ‎ Fixes COLDATA address.
• 05:2105:21, 6 May 2022 diff hist +598‎ PPU registers ‎ VRAM latching behavior.
• 04:4604:46, 6 May 2022 diff hist +78‎ PPU registers ‎ Further information on counter_latch behavior.
• 04:1204:12, 6 May 2022 diff hist +813‎ PPU registers ‎ Adds counter latching information (partly speculative). Existing documentation around this latching is incomplete and misleading. Also adds CGRAM latching information.
• 04:0604:06, 6 May 2022 diff hist +46‎ PPU pinout ‎ In order to explain counter latching behavior, EXTLATCH needs to be active low, not high.
• 00:5800:58, 6 May 2022 diff hist +21‎ PPU registers ‎ Mode 7 clarification. Formatting fixes.
• 00:3400:34, 6 May 2022 diff hist +1,038‎ PPU registers ‎ Corrections and clarifications around overlapping registers and value latches.

5 May 2022

• 11:2411:24, 5 May 2022 diff hist +2‎ m PPU registers ‎ Naming improvement.
• 11:2211:22, 5 May 2022 diff hist +76‎ PPU registers ‎ →‎STAT78 - PPU2 status flag and version ($213F read): Notes external latch flag read side effect and NTSC/PAL mode pin.
• 11:1311:13, 5 May 2022 diff hist +1,841‎ PPU registers ‎ Adds multiplication, counters, status registers.
• 10:0210:02, 5 May 2022 diff hist +2,456‎ PPU registers ‎ Adds scroll and mode 7 registers.

4 May 2022

• 09:0609:06, 4 May 2022 diff hist +2,212‎ PPU registers ‎ Adds VRAM and CGRAM registers.
• 04:3304:33, 4 May 2022 diff hist +2,337‎ PPU registers ‎ More registers. Some reformatting and formatting fixes.

27 April 2022

• 22:5622:56, 27 April 2022 diff hist −6‎ m APU pinout ‎ No need to mention CS and /CS in connector pinout.
• 12:5712:57, 27 April 2022 diff hist +15‎ APU pinout ‎ Improvements to sound module pinout.

26 April 2022

• 00:2600:26, 26 April 2022 diff hist +5‎ m PPU registers ‎ Improves mosaic size description.
• 00:1500:15, 26 April 2022 diff hist +22‎ m PPU registers ‎ Fixes mosaic size.
• 00:1200:12, 26 April 2022 diff hist −2‎ m PPU registers ‎ Minor fixes.
• 00:0300:03, 26 April 2022 diff hist +5,860‎ N PPU registers ‎ Starts the PPU registers page.

25 April 2022

• 05:2105:21, 25 April 2022 diff hist +18‎ m APU pinout ‎ Fixes Fievel Goes West title.
• 05:0505:05, 25 April 2022 diff hist +381‎ APU pinout ‎ Adds information about DSP input clock.
• 04:5104:51, 25 April 2022 diff hist +5,352‎ N Tricky-to-emulate games ‎ Adds Sour's tricky-to-emulate games findings.
• 02:0102:01, 25 April 2022 diff hist +7,794‎ N APU pinout ‎ Adds S-SMP and S-DSP pinouts.
• 01:5401:54, 25 April 2022 diff hist +383‎ CPU pinout ‎ Adds VPA, VDA, unknown clocks. Renames address and data pins to be more explicit.
• 01:1101:11, 25 April 2022 diff hist +138‎ Cartridge connector ‎ Renames CPU lines to be more explicit.

24 April 2022

• 23:5623:56, 24 April 2022 diff hist 0‎ PPU pinout ‎ Renames CPU lines to be more explicit.
• 04:5804:58, 24 April 2022 diff hist +269‎ PPU pinout ‎ Adds more test pin info and relevant reference.
• 01:2701:27, 24 April 2022 diff hist +192‎ PPU pinout ‎ Adds unknown direction to key.