User contributions for Fiskbit
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16 May 2022
- 05:2005:20, 16 May 2022 diff hist −20 m Offset-per-tile Minor clarity improvements (hopefully).
- 04:4504:45, 16 May 2022 diff hist +24 m Offset-per-tile Minor formatting changes.
13 May 2022
- 17:2517:25, 13 May 2022 diff hist +209 DMA registers Some clarity improvements. (Using n with a range instead of x for registers to make it clear there are 8 unique registers of each type, not 16 and not with any mirroring. Using x for readable unused bit and specifying it's unused, not open bus. Trying to make even more clear that the multi-address unused byte is just one byte at both addresses. Improving the pattern table.)
- 16:5716:57, 13 May 2022 diff hist −123 PPU registers Merges low and high byte registers into combined definitions. Fixes on-write description for VMDATAxREAD
9 May 2022
- 04:4704:47, 9 May 2022 diff hist +78 PPU registers Explicitly notes which registers require 2 accesses.
8 May 2022
- 09:5809:58, 8 May 2022 diff hist +47 PPU registers Some minor formatting changes and consistent, unambiguous units. Formatting is in flux at these early stages and I'd love feedback, particularly as we add more content and see what does or doesn't work well. (Also, thank you so much for contributing! I actually found this to be one of the more-confusing registers while building this page.)
6 May 2022
- 15:4715:47, 6 May 2022 diff hist +1,753 PPU registers Adds OAM registers.
- 07:1407:14, 6 May 2022 diff hist +239 N MediaWiki:Sidebar Updates the sidebar.
- 05:4605:46, 6 May 2022 diff hist +19 PPU registers Another attempt at clearly explaining mode 7 tilemap boundary behavior.
- 05:2405:24, 6 May 2022 diff hist 0 m PPU registers Fixes COLDATA address.
- 05:2105:21, 6 May 2022 diff hist +598 PPU registers VRAM latching behavior.
- 04:4604:46, 6 May 2022 diff hist +78 PPU registers Further information on counter_latch behavior.
- 04:1204:12, 6 May 2022 diff hist +813 PPU registers Adds counter latching information (partly speculative). Existing documentation around this latching is incomplete and misleading. Also adds CGRAM latching information.
- 04:0604:06, 6 May 2022 diff hist +46 PPU pinout In order to explain counter latching behavior, EXTLATCH needs to be active low, not high.
- 00:5800:58, 6 May 2022 diff hist +21 PPU registers Mode 7 clarification. Formatting fixes.
- 00:3400:34, 6 May 2022 diff hist +1,038 PPU registers Corrections and clarifications around overlapping registers and value latches.
5 May 2022
- 11:2411:24, 5 May 2022 diff hist +2 m PPU registers Naming improvement.
- 11:2211:22, 5 May 2022 diff hist +76 PPU registers →STAT78 - PPU2 status flag and version ($213F read): Notes external latch flag read side effect and NTSC/PAL mode pin.
- 11:1311:13, 5 May 2022 diff hist +1,841 PPU registers Adds multiplication, counters, status registers.
- 10:0210:02, 5 May 2022 diff hist +2,456 PPU registers Adds scroll and mode 7 registers.