User contributions for Fiskbit
From SNESdev Wiki
Jump to navigationJump to search
22 May 2022
- 19:3319:33, 22 May 2022 diff hist +106 MMIO registers Auto-read description improvement.
- 19:2619:26, 22 May 2022 diff hist +53 MMIO registers Clarity improvements.
- 18:2318:23, 22 May 2022 diff hist +314 MMIO registers More precision regarding joypad bits.
- 17:3917:39, 22 May 2022 diff hist +3,695 MMIO registers Adds joypad registers.
- 16:2916:29, 22 May 2022 diff hist +86 m MMIO registers 16-bit register formatting.
- 16:1316:13, 22 May 2022 diff hist 0 m MMIO registers Formatting improvements.
- 16:1116:11, 22 May 2022 diff hist +2,197 MMIO registers Adds interrupt-related CPU registers.
19 May 2022
- 18:2318:23, 19 May 2022 diff hist −13 m PPU pinout Removes duplicate section header.
16 May 2022
- 20:2020:20, 16 May 2022 diff hist +71 m PPU registers Expands gaps between bytes in register definitions to 3 characters (enough to support 2-digit bit names on both sides).
- 19:3519:35, 16 May 2022 diff hist +300 m DMA registers Uses fixed-width, non-wrapping text for target addresses.
- 18:0218:02, 16 May 2022 diff hist 0 m PPU registers Corrects TS register address.
- 17:5517:55, 16 May 2022 diff hist +23 PPU registers Changes register summary type field to be more mobile-friendly. Adds types for each definition of a register (to more clearly distinguish W8 from W16).
- 16:4716:47, 16 May 2022 diff hist +584 PPU registers Changes register summary table formatting to match those on the NESdev wiki. Prevents wrapping between nybbles of individual bytes. Adds bit letters after each named item. Breaks out BG1 and M7 scroll register bit definitions because they're separate registers at the same address.
- 05:2005:20, 16 May 2022 diff hist −20 m Offset-per-tile Minor clarity improvements (hopefully).
- 04:4504:45, 16 May 2022 diff hist +24 m Offset-per-tile Minor formatting changes.
13 May 2022
- 17:2517:25, 13 May 2022 diff hist +209 DMA registers Some clarity improvements. (Using n with a range instead of x for registers to make it clear there are 8 unique registers of each type, not 16 and not with any mirroring. Using x for readable unused bit and specifying it's unused, not open bus. Trying to make even more clear that the multi-address unused byte is just one byte at both addresses. Improving the pattern table.)
- 16:5716:57, 13 May 2022 diff hist −123 PPU registers Merges low and high byte registers into combined definitions. Fixes on-write description for VMDATAxREAD
9 May 2022
- 04:4704:47, 9 May 2022 diff hist +78 PPU registers Explicitly notes which registers require 2 accesses.
8 May 2022
- 09:5809:58, 8 May 2022 diff hist +47 PPU registers Some minor formatting changes and consistent, unambiguous units. Formatting is in flux at these early stages and I'd love feedback, particularly as we add more content and see what does or doesn't work well. (Also, thank you so much for contributing! I actually found this to be one of the more-confusing registers while building this page.)
6 May 2022
- 15:4715:47, 6 May 2022 diff hist +1,753 PPU registers Adds OAM registers.