APU register table: Difference between revisions

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(Create APU register table page)
 
(Add S-SMP register summary)
 
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== S-SMP registers ==
{| class="wikitable"
|+ S-SMP register summary
|-
! colspan=6 | S-SMP registers <small>([[APU register table/SMP|table source]])</small>
|-
! colspan=2 | Name
! Address
! Bits
! Type
! Notes
|-
{{:APU register table/SMP}}
|}
Register types:
* '''RW''' - Readable and Writable
* '''R''' - Readable
* '''W''' - Write only (reading will read back $00)
== S-DSP registers ==
== S-DSP registers ==


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== References ==
== References ==
* Anomie's SPC700 Doc
* Anomie's S-DSP Doc
* Anomie's S-DSP Doc
* ares source code, <tt>[https://github.com/ares-emulator/ares/tree/master/ares/sfc/smp ares/sfc/smp]</tt> directory, by Near and ares team
* ares source code, <tt>[https://github.com/ares-emulator/ares/tree/master/ares/sfc/dsp ares/sfc/dsp]</tt> directory, by Near and ares team
* ares source code, <tt>[https://github.com/ares-emulator/ares/tree/master/ares/sfc/dsp ares/sfc/dsp]</tt> directory, by Near and ares team

Latest revision as of 09:57, 8 November 2024

S-SMP registers

S-SMP register summary
S-SMP registers (table source)
Name Address Bits Type Notes
TEST Test $F0 IIEE TRWH W8 Undocumented test register.
CONTROL Control $F1 I.CC .210 W8 Enable IPL ROM (I), Clear data ports (C), timer enable (2,1,0).
DSPADDR Register Address $F2 RAAA AAAA RW8 Selects a DSP register address.
DSPDATA Register Data $F3 DDDD DDDD RW8 Reads or writes data to the selected DSP address.
CPUIO0 Port 0 $F4 DDDD DDDD RW8 Reads or writes data to APUIO0.
CPUIO1 Port 1 $F5 DDDD DDDD RW8 Reads or writes data to APUIO1.
CPUIO2 Port 2 $F6 DDDD DDDD RW8 Reads or writes data to APUIO2.
CPUIO3 Port 3 $F7 DDDD DDDD RW8 Reads or writes data to APUIO3.
--- $F8 .... .... RW8 Unused (normal RAM).
--- $F9 .... .... RW8 Unused (normal RAM).
T0TARGET Timer 0 $FA TTTT TTTT W8 8KHz timer 0 interval.
T1TARGET Timer 1 $FB TTTT TTTT W8 8KHz timer 1 interval.
T2TARGET Timer 2 $FC TTTT TTTT W8 64KHz timer 2 interval.
T0OUT Counter 0 $FD 0000 CCCC R8 Timer 0 count-up.
T1OUT Counter 1 $FE 0000 CCCC R8 Timer 1 count-up.
T2OUT Counter 2 $FF 0000 CCCC R8 Timer 2 count-up.

Register types:

  • RW - Readable and Writable
  • R - Readable
  • W - Write only (reading will read back $00)


S-DSP registers

S-DSP register summary
S-DSP global registers (table source)
Name Address Bits Type Notes
MVOLL MVOL (L) $0C VVVV VVVV RW Left channel main volume, signed.
MVOLR MVOL (R) $1C VVVV VVVV RW Right channel main volume, signed.
EVOLL EVOL (L) $2C VVVV VVVV RW Left channel echo volume, signed.
EVOLR EVOL (R) $3C VVVV VVVV RW Right channel main volume, signed.
KON $4C 7654 3210 RW Key on. Writing this with any bit set will start a new note for the corresponding voice.
KOFF KOF $5C 7654 3210 RW Key off. Writing this with any bit set will put the corresponding voice into its release state.
FLG $6C RMEN NNNN RW Flags: soft reset (R), mute all (M), echo disable (E), noise frequency (N).
ENDX $7C 7654 3210 R Read for end of sample flag for each channel.
EFB $0D VVVV VVVV RW Echo feedback, signed.
- - $1D ---- ---- RW Unused.
PMON $2D 7654 321- RW Enables pitch modulation for each channel, controlled by OUTX of the next lower channel.
NON $3D 7654 3210 RW For each channel, replaces the sample waveform with the noise generator output.
EON $4D 7654 3210 RW For each channel, sends to the echo unit.
DIR $5D DDDD DDDD RW Pointer to the sample source directory page at $DD00.
ESA $6D EEEE EEEE RW Pointer to the start of the echo memory region at $EE00.
EDL $7D ---- DDDD RW Echo delay time (D).
FIR0 C0 $0F VVVV VVVV RW Echo filter coefficient.
FIR1 C1 $1F VVVV VVVV RW Echo filter coefficient.
FIR2 C2 $2F VVVV VVVV RW Echo filter coefficient.
FIR3 C3 $3F VVVV VVVV RW Echo filter coefficient.
FIR4 C4 $4F VVVV VVVV RW Echo filter coefficient.
FIR5 C5 $5F VVVV VVVV RW Echo filter coefficient.
FIR6 C6 $6F VVVV VVVV RW Echo filter coefficient.
FIR7 C7 $7F VVVV VVVV RW Echo filter coefficient.
S-DSP voice registers (table source)
Name Address Bits Type Notes
VxVOLL VOL (L) $X0 SVVV VVVV RW Left channel volume, signed.
VxVOLR VOL (R) $X1 SVVV VVVV RW Right channel volume, signed.
VxPITCHL P (L) $X2 LLLL LLLL RW Low 8 bits of sample pitch.
VxPITCHH P (H) $X3 --HH HHHH RW High 6 bits of sample pitch.
VxSRCN SRCN $X4 SSSS SSSS RW Selects a sample source entry from the directory (see DIR below).
VxADSR1 ADSR (1) $X5 EDDD AAAA RW ADSR enable (E), decay rate (D), attack rate (A).
VxADSR2 ADSR (2) $X6 SSSR RRRR RW Sustain level (S), sustain rate (R).
VxGAIN GAIN $X7 0VVV VVVV
1MMV VVVV
RW Mode (M), value (V).
VxENVX ENVX $X8 0VVV VVVV R Reads current 7-bit value of ADSR/GAIN envelope.
VxOUTX OUTX $X9 SVVV VVVV R Reads signed 8-bit value of current sample wave multiplied by ENVX, before applying VOL.


Register types:

  • RW - Readable and Writable
  • R - Readable (technically writable, but not intended to be written to)


References

  • Anomie's SPC700 Doc
  • Anomie's S-DSP Doc
  • ares source code, ares/sfc/smp directory, by Near and ares team
  • ares source code, ares/sfc/dsp directory, by Near and ares team