User contributions for Fiskbit

3 June 2022

• 00:5800:58, 3 June 2022 diff hist 0‎ m CPU pinout ‎ Adds missing CPU prefix on A23. current

1 June 2022

• 04:1704:17, 1 June 2022 diff hist +599‎ Backgrounds ‎ Adds padding to priorities in BG mode table.
• 04:1304:13, 1 June 2022 diff hist +25‎ Sprites ‎ Notes which direction the priorities go in.

31 May 2022

• 11:5611:56, 31 May 2022 diff hist +9‎ m Errata ‎ More clarity on vblank NMI behavior.
• 11:5511:55, 31 May 2022 diff hist +249‎ Errata ‎ →‎Video: Further explains the behavior where enabling NMIs during vblank triggers an immediate NMI.
• 11:3211:32, 31 May 2022 diff hist +2‎ m Errata ‎ →‎References: Uses : to indent non-automated references to match automated ones.

30 May 2022

• 06:1106:11, 30 May 2022 diff hist 0‎ OAM layout ‎ Fixes sprite indices 0-15.

29 May 2022

• 00:3400:34, 29 May 2022 diff hist −3‎ MediaWiki:Sidebar ‎ Changes the SNES Discord link to make it more clear it's not run by NESdev staff. (Sidebar size limits prevent longer, more descriptive links here without ugly wrapping.) current

28 May 2022

• 08:2908:29, 28 May 2022 diff hist +2‎ m Mouse ‎ →‎References: Uses : to match indentation of automated references.

26 May 2022

• 07:4107:41, 26 May 2022 diff hist +856‎ WRAM pinout ‎ Names for connected signals, more signal descriptions, and corrections. current
• 04:4204:42, 26 May 2022 diff hist −2‎ m Tilemaps ‎ →‎Mode 7: Fix formatting.
• 04:3504:35, 26 May 2022 diff hist −2‎ m Tiles ‎ →‎8bpp Direct Color: Changes bit diagram so it doesn't suggest involvement of unrelated bits.
• 03:5203:52, 26 May 2022 diff hist +8‎ m Timing ‎ JOYSERn link formatting.
• 01:2701:27, 26 May 2022 diff hist +18‎ SNESdev Wiki ‎ →‎General: Adds CPU vectors link.
• 01:2401:24, 26 May 2022 diff hist +54‎ ROM header ‎ Adds interrupts back to the table as a single link to CPU vectors page.
• 01:2201:22, 26 May 2022 diff hist +16‎ CPU vectors ‎ Puts empty slots and ABORT into the tables.
• 01:0301:03, 26 May 2022 diff hist +26‎ ROM header ‎ Adds link to CPU vectors page.
• 01:0101:01, 26 May 2022 diff hist −722‎ ROM header ‎ Moves vectors to 'CPU vectors' page and adds $ prefix to addresses.
• 00:5600:56, 26 May 2022 diff hist +1,088‎ N CPU vectors ‎ Adds CPU vector page.

25 May 2022

• 23:3723:37, 25 May 2022 diff hist +72‎ Standard controller ‎ Notes the read behavior past first 16 reads.
• 23:3523:35, 25 May 2022 diff hist 0‎ m PPU registers ‎ →‎OAMADDL, OAMADDH - OAM word address ($2102, $2103 write): Fixes register address typo.
• 23:1623:16, 25 May 2022 diff hist −471‎ SNESdev Wiki ‎ Remove MediaWiki links that aren't relevant to standard contributors.
• 23:1423:14, 25 May 2022 diff hist +18‎ SNESdev Wiki ‎ →‎Pinouts: Adds WRAM pinout link.
• 23:1423:14, 25 May 2022 diff hist 0‎ m CPU pinout ‎ →‎Pinout: Minor formatting fix.
• 23:1323:13, 25 May 2022 diff hist 0‎ m PPU pinout ‎ →‎Pinout: Minor formatting fix.
• 23:1323:13, 25 May 2022 diff hist +2,454‎ N WRAM pinout ‎ Adds S-WRAM pinout.
• 09:3009:30, 25 May 2022 diff hist +466‎ MMIO registers ‎ →‎NMITIMEN - Interrupts and Joypad reading ($4200 write): Adds NMI details. Mentions the slight delay before auto-read starts. Improves auto-read description.
• 08:1208:12, 25 May 2022 diff hist +106‎ DMA registers ‎ Clarifies the DMA RAM copy limitation.
• 07:2807:28, 25 May 2022 diff hist +125‎ DMA registers ‎ Adds CPU and peripheral bus names to the intro. Elaborates a bit on what DMA is doing to explain why transfers must be cross-bus.
• 07:0607:06, 25 May 2022 diff hist −18‎ m Memory map ‎ Uses consistent, unambiguous units (KiB and MiB).
• 06:0906:09, 25 May 2022 diff hist +1‎ m DMA registers ‎ →‎NLTRn - HDMA Line-Counter ($43nA read/write) (n = 0..7): Adds missing n suffix to NLTR.
• 06:0806:08, 25 May 2022 diff hist 0‎ m MMIO register table/DMA ‎ Fixes register name: NTRL -> NLTR.
• 06:0806:08, 25 May 2022 diff hist 0‎ m DMA registers ‎ Fixes register name: NTRL -> NLTR.
• 06:0706:07, 25 May 2022 diff hist +400‎ DMA registers ‎ Adds power-on and reset info for each register.

24 May 2022

• 11:5911:59, 24 May 2022 diff hist +11‎ m DMA registers ‎ Notes n range in table.
• 11:5811:58, 24 May 2022 diff hist +1‎ m MMIO register table/MMIO ‎ Minor formatting changes for consistency.

23 May 2022

• 16:4016:40, 23 May 2022 diff hist −1‎ m MMIO registers ‎ Typo.
• 16:4016:40, 23 May 2022 diff hist +45‎ m MMIO registers ‎ Links to Division page. Minor reformatting.
• 16:0316:03, 23 May 2022 diff hist −89‎ m MMIO registers ‎ There are no 8x2 registers here.
• 15:2715:27, 23 May 2022 diff hist +127‎ m MMIO registers ‎ Adds back in accidentally-dropped sentence.
• 15:2515:25, 23 May 2022 diff hist +4,126‎ MMIO registers ‎ Adds register summary table, adds links to PPU and DMA register pages, and change some bit letters.
• 13:4613:46, 23 May 2022 diff hist +1,173‎ MMIO registers ‎ Adds fastROM enable, power-on and reset values, and more APU register and math register details.
• 12:3212:32, 23 May 2022 diff hist +1,528‎ MMIO registers ‎ Adds APU and S-WRAM registers.

22 May 2022

• 23:4323:43, 22 May 2022 diff hist +1‎ SNESdev Wiki ‎ Fixes MMIO registers link.
• 22:4722:47, 22 May 2022 diff hist +1,473‎ MMIO registers ‎ Adds math registers.
• 22:2522:25, 22 May 2022 diff hist 0‎ PPU registers ‎ Changes counter bit letters from X and Y to H and V.
• 22:2022:20, 22 May 2022 diff hist +6‎ m PPU registers ‎ Make signed descriptors consistent with rest of the page.
• 22:1822:18, 22 May 2022 diff hist +42‎ PPU registers ‎ Add signed descriptor to multiplication bit definitions.
• 21:5621:56, 22 May 2022 diff hist +6‎ m Controller reading ‎ Fixes register links.
• 21:5521:55, 22 May 2022 diff hist 0‎ m MMIO registers ‎ Fiskbit moved page CPU registers to MMIO registers without leaving a redirect: Concluded after discussion that 'CPU registers' is both too narrow and somewhat misleading.